ICS8432-111
700MH
Z
/350MH
Z
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
G
ENERAL
D
ESCRIPTION
The ICS8432-111 is a general purpose, dual output
Differential-to-3.3V LVPECL High Frequency Synthesizer.
The ICS8432-111 has a selectable differential CLK, nCLK
pair or LVCMOS/LVTTL TEST_CLK. The TEST_CLK input
accepts LVCMOS or LVTTL input levels and translates them
to 3.3V LVPECL levels. The CLK, nCLK pair can accept most
standard differential input levels.The VCO operates at a
frequency range of 200MHz to 700MHz. The VCO frequency
is programmed in steps equal to the value of the input differ-
ential or single ended reference frequency. Output frequen-
cies up to 700MHz for FOUT and 350MHz for FOUT/2 can be
programmed using the serial or parallel interfaces to the con-
figuration logic. The low phase noise characteristics and the
multiple frequency outputs of the ICS8432-111 makes it an
ideal clock source for Fibre Channel 1 and 2, and Infiniband
applications.
F
EATURES
•
Dual differential 3.3V LVPECL outputs
•
Selectable differential CLK, nCLK pair or LVCMOS TEST_CLK
•
CLK, nCLK pair can accept the following differential input
levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
•
TEST_CLK can accept the following input types:
LVCMOS or LVTTL
•
Maximum FOUT frequency: 700MHz
Maximum FOUT/2 frequency: 350MHz
•
CLK, nCLK or TEST_CLK input frequency: 40MHz
•
VCO range: 250MHz to 700MHz
•
Parallel or serial interface for programming counter
and VCO frequency multiplier and dividers
•
RMS period jitter: 5ps (maximum)
•
Cycle-to-cycle jitter: 40ps (maximum)
•
3.3V supply voltage
•
0°C to 70°C ambient operating temperature
•
Available in both standard (RoHS 5) and lead-free
(RoHS 6) packages
B
LOCK
D
IAGRAM
VCO_SEL
CLK_SEL
TEST_CLK
CLK
nCLK
0
1
P
IN
A
SSIGNMENT
VCO_SEL
nP_LOAD
nCLK
M4
M3
M2
M1
M0
32 31 30 29 28 27 26 25
M5
M6
M7
M8
N0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
TEST
V
CC
FOUT/2
nFOUT/2
V
CCO
FOUT
nFOUT
V
EE
24
23
22
CLK
TEST_CLK
CLK_SEL
V
CCA
S_LOAD
S_DATA
S_CLOCK
MR
ICS8432-111
21
20
19
18
17
PLL
PHASE DETECTOR
MR
÷M
VCO
0
1
÷
1
÷
2
÷
4
÷
8
÷
2
N1
nc
FOUT
nFOUT
FOUT/2
nFOUT/2
V
EE
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
N0:N1
CONFIGURATION
INTERFACE
LOGIC
TEST
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
8432CY-111
www.idt.com
1
REV. C OCTOBER 5, 2010
ICS8432-111
700MH
Z
/350MH
Z
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
F
UNCTIONAL
D
ESCRIPTION
NOTE: The functional description that follows describes op-
eration using a 25MHz clock input. Valid PLL loop divider
values for different input frequencies are defined in the Input
Frequency Characteristics, Table 5, NOTE 1.
The ICS8432-111 features a fully integrated PLL and there-
fore requires no external components for setting the loop band-
width. A differential clock input is used as the input to the
ICS8432-111. This input is fed into the phase detector. A
25MHz clock input provides a 25MHz phase detector refer-
ence frequency. The VCO of the PLL operates over a range
of 250MHz to 700MHz. The output of the M divider is also
applied to the phase detector.
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency by adjust-
ing the VCO control voltage. Note, that for some values of M
(either too high or too low), the PLL will not achieve lock. The
output of the VCO is scaled by a divider prior to being sent to
each of the LVPECL output buffers. The divider provides a
50% output duty cycle.
The programmable features of the ICS8432-111 support two
input modes to program the PLL M divider and N output divider.
The two input operational modes are parallel and serial.
Figure1
shows the timing diagram for each mode. In parallel mode, the
nP_LOAD input is initially LOW. The data on inputs M0 through
M8 and N0 and N1 is passed directly to the M divider and
N output divider. On the LOW-to-HIGH transition of the
nP_LOAD input, the data is latched and the M divider remains
loaded until the next LOW transition on nP_LOAD or until a se-
rial event occurs. As a result, the M and N bits can be hardwired
to set the M divider and N output divider to a specific default
state that will automatically occur during power-up. The TEST
output is LOW when operating in the parallel input mode. The
relationship between the VCO frequency, the input frequency
and the M divider is defined as follows: fVCO = f
IN
x M
The M value and the required values of M0 through M8 are shown
in Table 3B, Programmable VCO Frequency Function Table. When
the input clock is at 25MHz, the valid M values for which the
PLL will achieve lock are defined as 10
≤
M
≤
28. The frequency
out is defined as follows: fOUT = fVCO = f
IN
x M
N
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is
LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the shift
register are loaded into the M divider and N output divider when
S_LOAD transitions from LOW-to-HIGH. The M divide and N out-
put divide values are latched on the HIGH-to-LOW transition of
S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is
passed directly to the M divider and N output divider on each rising
edge of S_CLOCK. The serial mode can be used to
program the M and N bits and test bits T1 and T0. The internal reg-
isters T0 and T1 determine the state of the TEST output as follows:
T1
0
0
1
1
T0
0
1
0
1
TEST Output
LOW
S_Data, Shift Register Input
Output of M divider
CMOS Fout/2
S
ERIAL
L
OADING
S_CLOCK
S_DATA
T1
S_LOAD
T0
*
NULL
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
nP_LOAD
P
ARALLEL
L
OADING
M0:M8, N0:N1
nP_LOAD
M, N
S_LOAD
Time
F
IGURE
1. P
ARALLEL
& S
ERIAL
L
OAD
O
PERATIONS
*NOTE:
8432CY-111
The NULL timing slot must be observed.
www.idt.com
2
REV. C OCTOBER 5, 2010
ICS8432-111
700MH
Z
/350MH
Z
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2, 3, 4,
28, 29,
30, 31, 32
5, 6
7
8, 16
9
10
11,
12
13
14, 15
Name
M5
M6, M7, M8,
M0, M1,
M2, M3, M4
N0, N1
nc
V
EE
TEST
V
CC
FOUT/2,
nFOUT/2
V
CCO
FOUT, nFOUT
Input
Input
Input
Unused
Power
Output
Power
Output
Power
Output
Type
Pullup
M counter/divider inputs. Data latched on LOW-to-HIGH transistion
Pulldown of nP_LOAD input. LVCMOS/LVTTL interface levels.
Pulldown
Determines output divider value as defined in Table 3C
Function Table. LVCMOS/LVTTL interface levels.
No connect.
Negative supply pins.
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode. LVCMOS/LVTTL interface levels.
Core supply pin.
Half frequency differential output for the synthesizer.
3.3V LVPECL interface levels.
Output supply pin.
Differential output for the synthesizer. 3.3V LVPECL interface levels.
Active High Master Reset. When logic HIGH, the internal dividers
are reset causing the true outputs FOUTx to go low and the inver ted
outputs nFOUTx to go high. When logic LOW, the internal dividers
are the outputs are enabled. Asser tion of MR does not effect loaded
M, N, and T values. LVCMOS/LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register
on the rising edge of S_CLOCK. LVCMOS/LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge
of S_CLOCK. LVCMOS/LVTTL interface levels.
Controls transition of data from shift register into the dividers.
LVCMOS/LVTTL interface levels.
Analog supply pin.
Selects between differential clock input or test input as the PLL
reference source. LVCMOS/LVTTL interface levels. Selects CLK,
nCLK inputs when HIGH. Selects TEST_CLK when LOW.
Test clock input. LVCMOS/LVTTL interface levels.
Description
17
MR
Input
Pulldown
18
19
20
21
22
23
24
25
26
27
S_CLOCK
S_DATA
S_LOAD
V
CCA
CLK_SEL
TEST_CLK
CLK
nCLK
nP_LOAD
VCO_SEL
Input
Input
Input
Power
Input
Input
Input
Input
Input
Input
Pulldown
Pulldown
Pulldown
Pullup
Pulldown
Pullup
Pulldown Non-inver ting differential clock input.
Inver ting differential clock input.
Parallel load input. Determines when data present at M8:M0 is loaded
Pulldown into M divider, and when data present at N1:N0 sets the N output
divider value. LVCMOS/LVTTL interface levels.
Determines whether synthesizer is in PLL or bypass mode.
Pullup
LVCMOS/LVTTL interface levels.
NOTE:
Pullup
and
Pulldown
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
8432CY-111
www.idt.com
3
REV. C OCTOBER 5, 2010
ICS8432-111
700MH
Z
/350MH
Z
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
3A. P
ARALLEL
AND
S
ERIAL
M
ODE
F
UNCTION
T
ABLE
Inputs
Conditions
S_CLOCK
X
X
X
↑
L
L
X
↑
S_DATA
X
X
X
Data
Data
Data
X
Data
Reset. Forces outputs LOW.
Data on M and N inputs passed directly to the M
divider and N output divider. TEST output forced LOW.
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the M
divider and N output divider.
M divider and N output divider values are latched.
Parallel or serial input do not affect shift registers.
S_DATA passed directly to ripple counter as it is
clocked.
X
X
L
L
↑
↓
L
H
MR
H
L
L
L
L
L
L
L
nP_LOAD
X
L
↑
H
H
H
H
H
M
X
Data
Data
X
X
X
X
X
N
X
Data
Data
X
X
X
X
X
S_LOAD
NOTE: L = LOW
H = HIGH
X = Don't care
↑
= Rising edge transition
↓
= Falling edge transition
T
ABLE
3B. P
ROGRAMMABLE
VCO F
REQUENCY
F
UNCTION
T
ABLE
VCO Frequency
(MHz)
250
275
•
•
650
675
M Count
10
11
•
•
26
27
256
M8
0
0
•
•
0
0
128
M7
0
0
•
•
0
0
64
M6
0
0
•
•
0
0
32
M5
0
0
•
•
0
0
16
M4
0
0
•
•
1
1
8
M3
1
1
•
•
1
1
4
M2
0
0
•
•
0
0
2
M1
1
1
•
•
1
1
1
M0
0
1
•
•
0
1
700
28
0
0
0
0
1
1
1
0
0
NOTE 1: These M count values and the resulting frequencies correspond to differential input or TEST_CLK input frequency
of 25MHz.
T
ABLE
3C. P
ROGRAMMABLE
O
UTPUT
D
IVIDER
F
UNCTION
T
ABLE
Inputs
N1
0
0
1
1
N0
0
1
0
1
1
2
4
8
Output Frequency (MHz)
N Divider Value
Minimum
250
125
62.5
31.25
FOUT
Maximum
700
350
175
87.5
FOUT/2
Minimum
Maximum
125
62.5
31.25
15.625
350
175
87.5
43.75
8432CY-111
www.idt.com
4
REV. C OCTOBER 5, 2010
ICS8432-111
700MH
Z
/350MH
Z
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
CC
+ 0.5 V
50mA
100mA
47.9°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
140
15
Units
V
V
V
mA
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
Parameter
Input
High Voltage
VCO_SEL, CLK_SEL,
S_LOAD, S_DATA, S_CLOCK,
nP_LOAD, N0:N1, M0:M8, MR
TEST_CLK
Input
Low Voltage
VCO_SEL, CLK_SEL,
S_LOAD, S_DATA, S_CLOCK,
nP_LOAD, N0:N1, M0:M8, MR
TEST_CLK
M0-M4, M6-M8, N0, N1,
S_CLOCK, S_DATA, S_LOAD,
TEST_CLK, nP_LOAD, MR
M5, CLK_SEL, VCO_SEL
M0-M4, M6-M8, N0, N1,
S_CLOCK, S_DATA, S_LOAD,
TEST_CLK, nP_LOAD, MR
M5, CLK_SEL, VCO_SEL
V
OH
V
OL
Output
High Voltage
Output
Low Voltage
TEST; NOTE 1
TEST; NOTE 1
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V,
V
IN
= 0V
V
CC
= 3.465V,
V
IN
= 0V
-5
Test Conditions
Minimum
2
2
-0.3
Typical
Maximum
V
CC
+ 0.3
V
CC
+ 0.3
0.8
1.3
150
Units
V
V
V
V
µA
V
IH
V
IL
I
IH
Input
High Current
5
µA
I
IL
Input
Low Current
µA
-150
2.6
0.5
µA
V
V
NOTE 1: Outputs terminated with 50Ω to V
CCO
/2. See Parameter Information, 3.3V Output Load Test Circuit.
8432CY-111
www.idt.com
5
REV. C OCTOBER 5, 2010
京公网安备 11010802033920号
EEWORLD
