530FC479M000DGR datasheet, PDF

Datasheet> All Categories > Passive components> oscillator> 530FC479M000DGR

530FC479M000DGR: DescriptionLVDS Output Clock Oscillator, 479MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

530FC479M000DGR Overview

LVDS Output Clock Oscillator, 479MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

530FC479M000DGR Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
package instruction	ROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Code	unknown
Other features	TAPE AND REEL
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	7%
JESD-609 code	e4
Manufacturer's serial number	530
Installation features	SURFACE MOUNT
Nominal operating frequency	479 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVDS
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	2.75 V
Minimum supply voltage	2.25 V
Nominal supply voltage	2.5 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)
Base Number Matches	1

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

Synchronous motor full voltage starting circuit

Simple absolute value operation circuit

TDA1170D power amplifier circuit

15V, 5A regulated power supply composed of LM340T-15

ZVT three-phase Boost rectifier input circuit

Computer motherboard circuit diagram 815 1_35

Have you developed DM355 (Da Vinci)? Come in!: Recruiting developers with (DM355) development experience!...; 易晋生 Embedded System

100 points for questions, UC TCP/IP transplantation, as long as it is useful, give points: I wonder if anyone has ported UC TCP/IP to UCOS II? I have encountered many problems. One is that there is no relevant documentation and I don't know what the various files are used for. Another is wh...; mjwqh Embedded System

Notice on the 2011 Competition Registration Form, Division Overall Evaluation Form and Recommendation Form - from the official website of the competition: To all regional organizing committees and participating schools:Based on the suggestions of the national competition expert group, the National Competition Organizing Committee Secretariat has revised...; maylove Electronics Design Contest

Laptop optical drive removal and SSD installation: [color=#000][font=Arial][size=4]I have been using my laptop for almost four years. I feel that it is lagging when I open some large software such as AD13 and CCS. I see that the price of SSD has dropp...; 数码小叶 Talking

Merry Christmas! We always melt in those ordinary yet profound touches: We will always melt in those ordinary yet profound touches. No matter how much time has passed, we will always remember that there was someone who once held our hands warmly and walked us through sadn...; soso Talking

Ask a basic question: What do these IO states mean?: From the 2410 data sheet I/O State: @BUS REQ: Hi-z, P, –/–, I, O, –/–/–, – I/O State: @PWR-off: O(L)/–, O(L)/–/–, –/Hi-z/– I/O State: @nRESET: AI, AO I/O Type: t8 s3o d3o s3i d1c us s3o What do these ...; gga Embedded System

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components