ICS8735I-21
700MH
Z
, D
IFFERENTIAL
-
TO
-3.3V LVPECL
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
G
ENERAL
D
ESCRIPTION
The ICS8735I-21 is a highly versatile 1:1 Differential-to-
3.3V LVPECL clock generator. The CLK, nCLK pair can
accept most standard differential input levels. The
ICS8735I-21 has a fully integrated PLL and can be config-
ured as zero delay buffer, multiplier or divider, and has an
output frequency range of 31.25MHz to 700MHz. The ref-
erence divider, feedback divider and output divider
are each programmable, thereby allowing for the following
output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4,
1:8. The external feedback allows the device to achieve
“zero delay” between the input clock and the output clocks.
The PLL_SEL pin can be used to bypass the PLL for
system test and debug purposes. In bypass mode, the
reference clock is routed around the PLL and into the
internal output dividers.
F
EATURES
•
One differential 3.3V LVPECL output pair,
one differential feedback output pair
•
Differential CLK, nCLK input pair
•
CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
•
Output frequency range: 31.25MHz to 700MHz
•
Input frequency range: 31.25MHz to 700MHz
•
VCO range: 250MHz to 700MHz
•
Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
•
External feedback for “zero delay” clock regeneration
with configurable frequencies
•
Cycle-to-cycle jitter: 40ps (maximum)
•
Static phase offset: 50ps ± 150ps
•
3.3V supply voltage
•
-40°C to 85°C ambient operating temperature
•
Available in both standard and lead-free RoHS compliant
packages
B
LOCK
D
IAGRAM
PLL_SEL
÷1, ÷2, ÷4, ÷8,
÷16, ÷32, ÷64
P
IN
A
SSIGNMENT
0
1
Q
nQ
QFB
nQFB
CLK
nCLK
MR
V
CC
nFB_IN
FB_IN
SEL2
V
EE
nQFB
QFB
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
nc
SEL1
SEL0
V
CC
PLL_SEL
V
CCA
SEL3
V
CCO
Q
nQ
CLK
nCLK
PLL
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
FB_IN
nFB_IN
ICS8735I-21
20-Lead, 300-MIL SOIC
7.5mm x 12.8mm x 2.3mm body package
M Package
Top View
SEL0
SEL1
SEL2
SEL3
MR
8735AMI-21
www.idt.com
1
REV. C AUGUST 11, 2010
ICS8735I-21
700MH
Z
, D
IFFERENTIAL
-
TO
-3.3V LVPECL
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3
4, 17
5
6
7
8
9, 10
11, 12
13
14
15
16
18
19
20
Name
CLK
nCLK
MR
V
CC
nFB_IN
FB_IN
SEL2
V
EE
nQFB,
QFB
nQ, Q
V
CCO
SEL3
V
CCA
PLL_SEL
SEL0
SEL1
nc
Input
Input
Input
Power
Input
Input
Input
Power
Output
Output
Power
Input
Power
Input
Input
Input
Unused
Type
Pullup
Description
Pulldown Non-inver ting differential clock input.
Inver ting differential clock input.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Q and QFB to go low and the inver ted outputs nQ
Pulldown
and nQFB to go high. When LOW, the internal dividers and the outputs are
enabled. LVCMOS / LVTTL interface levels.
Core supply pins.
Feedback input to phase detector for regenerating clocks with "zero delay".
Pullup
Connect to pin 9.
Feedback input to phase detector for regenerating clocks with "zero delay".
Pulldown
Connect to pin 10.
Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
Negative supply pin.
Differential feedback outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Output supply pin.
Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
Analog supply pin.
Selects between the PLL and reference clock as the input to the dividers.
Pullup
When LOW, selects reference clock. When HIGH, selects PLL.
LVCMOS / LVTTL interface levels.
Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
No connect.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
8735AMI-21
www.idt.com
2
REV. C AUGUST 11, 2010
ICS8735I-21
700MH
Z
, D
IFFERENTIAL
-
TO
-3.3V LVPECL
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Inputs
SEL3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Reference Frequency Range (MHz)*
250 - 700
125 - 350
62.5 - 175
31.25 - 87.5
250 - 700
125 - 350
62.5 - 175
250 - 700
125 - 350
250 - 700
125 - 350
62.5 - 175
31.25 - 87.5
62.5 - 175
31.25 - 87.5
31.25 - 87.5
Outputs
PLL_SEL = 1
PLL Enable Mode
Q, nQ; QFB, nQFB
÷1
÷1
÷1
÷1
÷2
÷2
÷2
÷4
÷4
÷8
x2
x2
x2
x4
x4
x8
*NOTE: VCO frequency range for all configurations above is 250MHz to 700MHz.
T
ABLE
3B. PLL B
YPASS
F
UNCTION
T
ABLE
Inputs
SEL3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
8735AMI-21
SEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
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3
SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Outputs
PLL_SEL = 0
PLL Bypass Mode
Q, nQ; QFB, nQFB
÷4
÷4
÷4
÷8
÷8
÷8
÷ 16
÷ 16
÷ 32
÷ 64
÷2
÷2
÷4
÷1
÷2
÷1
REV. C AUGUST 11, 2010
ICS8735I-21
700MH
Z
, D
IFFERENTIAL
-
TO
-3.3V LVPECL
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
CC
Outputs, V
CCO
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
CC
+ 0.5 V
-0.5V to V
CCO
+ 0.5V
46.2°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
150
15
Units
V
V
V
mA
mA
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol Parameter
V
IH
V
IL
I
IH
Input High Voltage
Input Low Voltage
Input High Current
SEL0, SEL1, SEL2,
SEL3, MR
PLL_SEL
SEL0, SEL1, SEL2,
SEL3, MR
PLL_SEL
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-5
-150
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
CC
+ 0.3
0.8
150
5
Units
V
V
µA
µA
µA
µA
I
IL
Input Low Current
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol Parameter
I
IH
I
IL
V
PP
Input High Current
Input Low Current
CLK, FB_IN
nCLK, nFB_IN
CLK, FB_IN
nCLK, nFB_IN
Test Conditions
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-5
-150
0.15
1.3
V
CC
- 0.85
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1, 2
V
EE
+ 0.5
V
CMR
NOTE 1: Common mode voltage is defined as V
IH
.
NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is V
CC
+ 0.3V.
8735AMI-21
www.idt.com
4
REV. C AUGUST 11, 2010
ICS8735I-21
700MH
Z
, D
IFFERENTIAL
-
TO
-3.3V LVPECL
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
T
ABLE
4D. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CCO
- 1.4
V
CCO
- 2.0
0.6
Typical
Maximum
V
CCO
- 0.9
V
CCO
- 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50
Ω
to V
CCO
- 2V.
T
ABLE
5. I
NPUT
F
REQUENCY
C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
f
IN
Parameter
Input Frequency
CLK, nCLK
Test Conditions
PLL_SEL = 1
PLL_SEL = 0
Minimum
31.25
Typical
Maximum
700
700
Units
MHz
MHz
T
ABLE
6. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
f
MAX
t
PD
tsk(o)
t
(Ø)
t
jit(cc)
t
jit(
θ)
t
L
t
R
/ t
F
Parameter
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 4, 5
Static Phase Offset; NOTE 2, 5
Cycle-to-Cycle Jitter; NOTE 5, 6
Phase Jitter; NOTE 3, 5, 6
PLL Lock Time
Output Rise/Fall Time
20% to 80%
200
PLL_SEL = 0V,
f
≤
700MHz
PLL_SEL = 0V
PLL_SEL = 3.3V
2.8
Test Conditions
Minimum
Typical
Maximum
700
4.9
35
200
40
±65
1
700
Units
MHz
ns
ps
ps
ps
ps
ms
ps
%
-100
50
odc
Output Duty Cycle
47
53
All parameters measured at f
MAX
unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal,
when the PLL is locked and the input reference frequency is stable.
NOTE 3: Phase jitter is dependent on the input source used.
NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential crosspoints.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Characterized at VCO frequency of 622MHz.
8735AMI-21
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5
REV. C AUGUST 11, 2010
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