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74AUP2G00GD-G

Description
IC,LOGIC GATE,DUAL 2-INPUT NAND,CMOS,LLCC,8PIN,PLASTIC
Categorylogic    logic   
File Size489KB,17 Pages
ManufacturerNXP
Websitehttps://www.nxp.com
Environmental Compliance
Download Datasheet Parametric View All

74AUP2G00GD-G Overview

IC,LOGIC GATE,DUAL 2-INPUT NAND,CMOS,LLCC,8PIN,PLASTIC

74AUP2G00GD-G Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerNXP
package instructionSON, SOLCC8,.11,20
Reach Compliance Codeunknown
JESD-30 codeR-PDSO-N8
Load capacitance (CL)30 pF
Logic integrated circuit typeNAND GATE
MaximumI(ol)0.0017 A
Number of terminals8
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeSON
Encapsulate equivalent codeSOLCC8,.11,20
Package shapeRECTANGULAR
Package formSMALL OUTLINE
power supply1.2/3.3 V
Prop。Delay @ Nom-Sup24.9 ns
Certification statusNot Qualified
Schmitt triggerNO
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal formNO LEAD
Terminal pitch0.5 mm
Terminal locationDUAL
Base Number Matches1
74AUP2G00
Low-power dual 2-input NAND gate
Rev. 04 — 5 June 2008
Product data sheet
1. General description
The 74AUP2G00 provides the dual 2-input NAND function.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V
CC
range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
V
CC
range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing a damaging backflow current through the device
when it is powered down.
2. Features
I
Wide supply voltage range from 0.8 V to 3.6 V
I
High noise immunity
I
Complies with JEDEC standards:
N
JESD8-12 (0.8 V to 1.3 V)
N
JESD8-11 (0.9 V to 1.65 V)
N
JESD8-7 (1.2 V to 1.95 V)
N
JESD8-5 (1.8 V to 2.7 V)
N
JESD8-B (2.7 V to 3.6 V)
I
ESD protection:
N
HBM JESD22-A114E Class 3A exceeds 5000 V
N
MM JESD22-A115-A exceeds 200 V
N
CDM JESD22-C101C exceeds 1 000 V
I
Low static power consumption; I
CC
= 0.9
µA
(maximum)
I
Latch-up performance exceeds 100 mA per JESD78 Class II
I
Inputs accept voltages up to 3.6 V
I
Low noise overshoot and undershoot < 10 % of V
CC
I
I
OFF
circuitry provides partial Power-down mode operation
I
Multiple package options
I
Specified from
−40 °C
to +85
°C
and
−40 °C
to +125
°C
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