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74VHC164 — 8-Bit Serial-In, Parallel-Out Shift Register
February 2008
74VHC164
8-Bit Serial-In, Parallel-Out Shift Register
Features
■
High Speed: f
MAX
=
175MHz at V
CC
=
5V
■
Low power dissipation: I
CC
=
4µA (max.) at T
A
=
25°C
■
High noise immunity: V
NIH
=
V
NIL
=
28% V
CC
(min.)
■
Power down protection provided on all inputs
■
Low noise: V
OLP
=
0.8V (max.)
■
Pin and function compatible with 74HC164
General Description
The VHC164 is an advanced high-speed CMOS device
fabricated with silicon gate CMOS technology. It
achieves the high-speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low
power dissipation. The VHC164 is a high-speed 8-Bit
Serial-In/Parallel-Out Shift Register. Serial data is
entered through a 2-input AND gate synchronous with
the LOW-to-HIGH transition of the clock. The device fea-
tures an asynchronous Master Reset which clears the
register, setting all outputs LOW independent of the
clock. An input protection circuit insures that 0V to 7V
can be applied to the input pins without regard to the
supply voltage. This device can be used to interface 5V
to 3V systems and two supply systems such as battery
backup. This circuit prevents device destruction due to
mismatched supply and input voltages.
Ordering Information
Order Number
74VHC164M
74VHC164SJ
74VHC164MTC
74VHC164N
Package
Number
M14A
M14D
MTC14
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"
Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1993 Fairchild Semiconductor Corporation
74VHC164 Rev. 1.4.0
www.fairchildsemi.com
74VHC164 — 8-Bit Serial-In, Parallel-Out Shift Register
Connection Diagram
Logic Symbol
Function Table
Pin Description
Pin
Names
A, B
CP
MR
Q
0
–Q
7
Data Inputs
Clock Pulse Input (Active Rising Edge)
Master Reset Input (Active LOW)
Outputs
Description
Operating
Mode
Reset (Clear)
Shift
Inputs
MR
L
H
H
H
H
Outputs
B
X
L
H
L
H
A
X
L
L
H
H
Q
0
L
L
L
L
H
Q
1
–Q
7
L–L
Q
0
–Q
6
Q
0
–Q
6
Q
0
–Q
6
Q
0
–Q
6
H
=
HIGH Voltage Levels
Functional Description
The VHC164 is an edge-triggered 8-bit shift register with
serial data entry and an output from each of the eight
stages. Data is entered serially through one of two inputs
(A or B); either of these inputs can be used as an active
High Enable for data entry through the other input. An
unused input must be tied HIGH.
Each LOW-to-HIGH transition on the Clock (CP) input
shifts data one place to the right and enters into Q
0
the
logical AND of the two data inputs (A • B) that existed
before the rising clock edge. A LOW level on the Master
Reset (MR) input overrides all other inputs and clears
the register asynchronously, forcing all Q outputs LOW.
L
=
LOW Voltage Levels
X
=
Immaterial
Q
=
Lower case letters indicate the state of the
referenced input or output one setup time prior to
the LOW-to-HIGH clock transition.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
©1993 Fairchild Semiconductor Corporation
74VHC164 Rev. 1.4.0
www.fairchildsemi.com
2
74VHC164 — 8-Bit Serial-In, Parallel-Out Shift Register
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
V
IN
V
OUT
I
IK
I
OK
I
OUT
I
CC
T
STG
T
L
Supply Voltage
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC V
CC
/ GND Current
Storage Temperature
Parameter
Rating
–0.5V to +7.0V
–0.5V to +7.0V
–0.5V to V
CC
+ 0.5V
–20mA
±20mA
±25mA
±75mA
–65°C to +150°C
260°C
Lead Temperature (Soldering, 10 seconds)
Recommended Operating Conditions
(1)
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
V
CC
V
IN
V
OUT
T
OPR
t
r
, t
f
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time,
V
CC
=
3.3V ± 0.3V
V
CC
=
5.0V ± 0.5V
Parameter
Rating
2.0V to 5.5V
0V to +5.5V
0V to V
CC
–40°C to +85°C
0ns/V
∼
100ns/V
0ns/V
∼
20ns/V
Note:
1. Unused inputs must be held HIGH or LOW. They may not float.
©1993 Fairchild Semiconductor Corporation
74VHC164 Rev. 1.4.0
www.fairchildsemi.com
3
74VHC164 — 8-Bit Serial-In, Parallel-Out Shift Register
DC Electrical Characteristics
T
A
=
25°C
Symbol
V
IH
V
IL
V
OH
T
A
=
–40°C to
+85°C
Max.
Min.
1.50
0.7 x V
CC
0.50
0.3 x V
CC
0.50
0.3 x V
CC
1.9
2.9
4.4
2.48
3.80
V
V
Parameter
HIGH Level Input
Voltage
LOW Level Input
Voltage
HIGH Level
Output Voltage
V
CC
(V)
2.0
3.0–5.5
2.0
3.0–5.5
2.0
3.0
4.5
3.0
4.5
Conditions
Min.
1.50
0.7 x V
CC
Typ.
Max.
Units
V
V
IN
=
V
IH
or V
IL
I
OH
=
–50µA
1.9
2.9
4.4
2.0
3.0
4.5
I
OH
=
–4mA
I
OH
=
–8mA
V
IN
=
V
IH
or V
IL
I
OL
=
50µA
2.58
3.94
0.0
0.0
0.0
0.1
0.1
0.1
0.36
0.36
±0.1
4.0
V
OL
LOW Level
Output Voltage
2.0
3.0
4.5
3.0
4.5
0.1
0.1
0.1
0.44
0.44
±1.0
40.0
V
I
OL
=
4mA
I
OL
=
8mA
V
IN
=
5.5V or GND
V
IN
=
V
CC
or GND
I
IN
I
CC
Input Leakage
Current
Quiescent
Supply Current
0–5.5
5.5
µA
µA
Noise Characteristics
T
A
=
25°C
Symbol
V
OLP(2)
V
OLV(2)
V
IHD(2)
V
ILD(2)
Parameter
Quiet Output Maximum
Dynamic V
OL
Quiet Output Minimum
Dynamic V
OL
Minimum HIGH Level
Dynamic Input Voltage
Maximum LOW Level
Dynamic Input Voltage
V
CC
(V)
5.0
5.0
5.0
5.0
Conditions
C
L
=
50pF
C
L
=
50pF
C
L
=
50pF
C
L
=
50pF
Typ.
0.5
–0.5
Limits
0.8
–0.8
3.5
1.5
Units
V
V
V
V
Note:
2. Parameter guaranteed by design.
©1993 Fairchild Semiconductor Corporation
74VHC164 Rev. 1.4.0
www.fairchildsemi.com
4
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