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A54SX32CQ208B

Description
FPGA, 2880 CLBS, 32000 GATES, 205MHz, CQFP208, CERAMIC, QFP-208
CategoryProgrammable logic devices    Programmable logic   
File Size377KB,46 Pages
ManufacturerMicrosemi
Websitehttps://www.microsemi.com
Download Datasheet Parametric View All

A54SX32CQ208B Overview

FPGA, 2880 CLBS, 32000 GATES, 205MHz, CQFP208, CERAMIC, QFP-208

A54SX32CQ208B Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerMicrosemi
package instructionQFF, TPAK208,2.9SQ,20
Reach Compliance Codecompliant
ECCN code3A001.A.2.C
Other features48000 SYSTEM GATES AVAILABLE
maximum clock frequency205 MHz
Combined latency of CLB-Max1 ns
JESD-30 codeS-CQFP-F208
JESD-609 codee0
length29.21 mm
Configurable number of logic blocks2880
Equivalent number of gates32000
Number of entries246
Number of logical units2880
Output times246
Number of terminals208
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize2880 CLBS, 32000 GATES
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeQFF
Encapsulate equivalent codeTPAK208,2.9SQ,20
Package shapeSQUARE
Package formFLATPACK
Peak Reflow Temperature (Celsius)225
power supply3.3,5 V
Programmable logic typeFIELD PROGRAMMABLE GATE ARRAY
Certification statusNot Qualified
Filter levelMIL-STD-883 Class B
Maximum seat height3.06 mm
Maximum supply voltage3.63 V
Minimum supply voltage2.97 V
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formFLAT
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature20
width29.21 mm
Base Number Matches1
v2.1
SX Family FPGAs RadTolerant and HiRel
Features
RadTolerant SX Family
Tested Total Ionizing Dose (TID) Survivability Level
Radiation Performance to 100 Krads (Si) (I
CC
Standby
Parametric)
Devices Available from Tested Pedigreed Lots
Up to 160 MHz On-Chip Performance
Offered as Class B and E-Flow (Actel Space Level
Flow)
QMl Certified Devices
High Density Devices
16,000 and 32,000 Available Logic Gates
Up to 225 User I/Os
Up to 1,080 Dedicated Flip-Flops
Easy Logic Integration
Nonvolatile, User Programmable
Highly Predictable Performance with 100%
Automatic Place-and-Route
100% Resource Utilization with 100% Pin Locking
Mixed Voltage Support – 3.3 V Operation with 5.0 V
Input Tolerance for Low-Power Operation
JTAG Boundary Scan Testing in Compliance with IEEE
Standard 1149.1
Secure Programming Technology Prevents Reverse
Engineering and Design Theft
Permanently Programmed for Operation on Power-
Up
Unique In-System Diagnostic and Debug Facility with
Silicon Explorer
Software Design Support with Actel Designer and
Libero
®
Integrated Design Environment (IDE) Tools
Predictable, Reliable, and Permanent Antifuse
Technology Performance
HiRel SX Family
Fastest HiRel FPGA Family Available
Up to 240 MHz On-Chip Performance
Low Cost Prototyping Vehicle for RadTolerant
Devices
Offered as Commercial or Military Temperature
Tested and Class B
Cost Effective QML MIL-Temp Plastic Packaging
Options
Standard Hermetic Packaging Offerings
QML Certified Devices
Product Profile
Device
Capacity
System Gates
Logic Gates
Logic Modules
Register Cells
Combinatorial Cells
User I/Os (Maximum)
JTAG
Packages (by pin count)
CQFP
RT54SX16
(Obsolete)
24,000
16,000
1,452
528
924
179
Yes
208, 256
A54SX16
24,000
16,000
1,452
528
924
180
Yes
208, 256
RT54SX32
(Obsolete)
48,000
32,000
2,880
1,080
1,800
227
Yes
208, 256
A54SX32
48,000
32,000
2,880
1,080
1,800
228
Yes
208, 256
March 2005
© 2005 Actel Corporation
i
See Actel’s website for the latest version of the datasheet.

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