7809LPRPFH datasheet, PDF - EEWORLD Datasheet

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7809LPRPFH: DescriptionADC, Successive Approximation, 16-Bit, 1 Func, 3 Channel, Serial Access, CMOS, FP-24; CategoryAnalog mixed-signal IC converter; File Size234KB，23 Pages; ManufacturerMaxwell Technologies Inc.

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7809LPRPFH Overview

ADC, Successive Approximation, 16-Bit, 1 Func, 3 Channel, Serial Access, CMOS, FP-24

7809LPRPFH Parametric

Parameter Name	Attribute value
Maker	Maxwell Technologies Inc.
Parts packaging code	DFP
package instruction	QFF, FL24,.4
Contacts	24
Reach Compliance Code	compliant
ECCN code	EAR99
Maximum analog input voltage	10 V
Minimum analog input voltage	-10 V
Maximum conversion time	8 µs
Converter type	ADC, SUCCESSIVE APPROXIMATION
JESD-30 code	R-XDFP-F24
length	15.1384 mm
Maximum linear error (EL)	0.0046%
Number of analog input channels	3
Number of digits	16
Number of functions	1
Number of terminals	24
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output bit code	BINARY, 2\'S COMPLEMENT BINARY
Output format	SERIAL
Package body material	UNSPECIFIED
encapsulated code	QFF
Encapsulate equivalent code	FL24,.4
Package shape	RECTANGULAR
Package form	FLATPACK
power supply	5 V
Certification status	Not Qualified
Sampling rate	0.1 MHz
Sample and hold/Track and hold	SAMPLE
Maximum seat height	7.6708 mm
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	FLAT
Terminal pitch	1.27 mm
Terminal location	DUAL
total dose	100k Rad(Si) V
width	10.16 mm
Base Number Matches	1

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16-Bit Latchup Protected

Analog to Digital Converter

7809LP

R/C

POWER DOWN

Successive Approximation Register and Control Logic

Clock

CDAC

20 kΩ

10 kΩ

5 kΩ

20 kΩ

Comparator

Serial Data

Out

Data

Clock

Serial

Data

BUSY

CAP

Buffer

4 kΩ

REF

Internal

+2.5V Ref.

Memory

Logic Diagram

EATURES

• R

-P

® radiation-hardened against natural space radia-

tion

• Total dose hardness:

- > 100 krad (Si), depending upon space mission

• Latch-up Protection Technology (LPT

)

• SEL converted into a reset

- Rate based on cross section and mission

• Same footprint as ADS7809

• Package: 24 pin R

-P

flat package

• 100 kHz min sampling rate

• ±10 V and 0 V to 5 V input range

• Advanced CMOS technology

• DNL: 16-bits “No Missing Codes”

• 83 dB min SINAD with 20 kHz input

• Single +5 V supply operation

• Utilizes internal or external reference

• Serial output

• Power dissipation: 132 mW max

ESCRIPTION

Maxwell Technologies’ 7809LP high-speed 16-bit analog to

digital converter features a greater than 100 kilorad (Si) total

dose tolerance depending upon space mission. Using Max-

well’s radiation-hardened R

-P

® packaging technology, the

7809LP has the same footprint as ADS7809 and is latchup

protected by Maxwell Technologies’ Latchup Protection Tech-

nology (LPT

). It is a 24 pin, 16-bit sampling analog-to-digital

converter using state-of-the-art CMOS structures. The

7809LP contains a 16-bit capacitor based SAR A/D with S/H,

reference, clock, interface for microprocessor use, and serial

output drivers. The 7809LP is specified at a 100kHz sampling

rate, and guaranteed over the full temperature range. Laser-

trimmed scaling resistors provide various input ranges include

±10 V and 0 to 5 V, while the innovative design allows opera-

tion from a single +5 V supply, with power dissipation of under

132 mW.

Maxwell Technologies' patented R

-P

packaging technol-

ogy incorporates radiation shielding in the microcircuit pack-

age. It eliminates the need for box shielding while providing

the required radiation shielding for a lifetime in orbit or space

mission. In a GEO orbit, R

-P

provides greater than 100

krad (Si) radiation dose tolerance. This product is available

with screening up to Class K.

02.18.02 Rev 4

All data sheets are subject to change without notice

(858) 503-3300- Fax: (858) 503-3301 - www.maxwell.com

16-Bit Latchup Protected Analog to Digital Converter

ABLE

1. 7809LP P

ESCRIPTION

YMBOL

R1IN

AGND1

R2IN

R3IN

CAP

REF

AGND2

SB/BTC

Analog Input.

Analog Ground. Used internally as ground reference point.

Analog Input.

Reference Buffer Capacitor. 2.2 µ F tantalum to ground.

Reference Input/Output. 2.2 µ F tantalum capacitor to ground.

Analog Ground.

ESCRIPTION

7809LP

Select Straight Binary or Binary Two’s Complement data output format. If HIGH, data will be

output in a Straight Binary format. If LOW, data will be output in a Binary Two’s Complement

format.

Select External or Internal Clock for transmitting data. If HIGH, data will be output synchronized

to the clock input on DATACLK. If LOW, a convert command will initiate the transmission of the

data from the previous conversion, along with 16 clock pulses output on DATACLK.

Digital Ground.

Built In test function of the latchup protection. Drive LOW during normal operation.

EXT/INT

Memory

DGND

LPBIT

LPSTATUS Latchup Protection Status Output. LPSTATUS when HIGH indicates latchup protection is

active and output data is invalid.

VANA

VDIG

SYNC

DATACLK

Analog Supply Input. Nominally 5V.

Digital Supply Input. Nominally 5V.

Sync Output. If EXT/INT is HIGH, either a rising edge on R/C with CS LOW or a falling edge on

CS with R/C HIGH will output a pulse on SYNC synchronized to the external DATACLK.

Either an input or an output depending on the EXT/INT level. Output data will be synchronized

to this clock. If EXT/INT is LOW, DATACLK will transmit 16 pulses after each conversion, and

then remain LOW between conversions.

Serial Data Output. Data will be synchronized to DATACLK, with the format determined by the

level of SB/BTC. In the external clock mode, after 16-bits of data, the 7809LOPO will output the

level input of TAG as long as CS is LOW and R/C is HIGH. If EXT/INT is LOW, data will be valid

on both the rising and falling edges of DATACLK, and between conversions DATA will stay at

the level of the TAG input when the conversion was started.

Tag input for use in external clock mode. If EXT/INT is HIGH, the digital data input on TAG will

be output on DATA with a delay of 16 DATACLK pulses as long as CS is LOW and R/C is

HIGH.

Read/Convert Input. With CS LOW, a falling edge on R/C puts the internal sample/hold into the

hold state and starts a conversion. When EXT/INT is LOW, this also initiates the transmission

of the data results from the previous conversion. If EXT/INT is HIGH, a rising edge on R/C with

CS LOW, or a falling edge on CS with R/C HIGH, transmits a pulse on SYNC and initiates the

transmission of data from the previous conversion.

Chip Select. Internally OR’ed with R/C.

DATA

TAG

R/C

02.18.02 Rev 4

All data sheets are subject to change without notice

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