LC
2
MOS
Quad 14-Bit DACs
AD7834/AD7835
FEATURES
Four 14-bit DACs in one package
AD7834—serial loading
AD7835—parallel 8-bit/14-bit loading
Voltage outputs
Power-on reset function
Maximum/minimum output voltage range of ±8.192 V
Maximum output voltage span of 14 V
Common voltage reference inputs
User-assigned device addressing
Clear function to user-defined voltage
Surface-mount packages
AD7834—28-lead SOIC and PDIP
AD7835—44-lead MQFP and PLCC
into one via DIN, SCLK, and FSYNC. The AD7834 has five
dedicated package address pins, PA0 to PA4, that can be wired
to AGND or V
CC
to permit up to 32 AD7834s to be individually
addressed in a multipackage application.
The AD7835 can accept either 14-bit parallel loading or double-
byte loading, where right-justified data is loaded in one 8-bit
byte and one 6-bit byte. Data is loaded from the external bus
into one of the input latches under the control of the WR, CS,
BYSHF, and DAC channel address pins, A0 to A2.
With each device, the LDAC signal is used to update all four
DAC outputs simultaneously, or individually, on reception of
new data. In addition, for each device, the asynchronous CLR
input can be used to set all signal outputs, V
OUT
1 to V
OUT
4, to
the user-defined voltage level on the device sense ground pin,
DSG. On power-on, before the power supplies have stabilized,
internal circuitry holds the DAC output voltage levels to within
±2 V of the DSG potential. As the supplies stabilize, the DAC
output levels move to the exact DSG potential (assuming CLR is
exercised).
The AD7834 is available in a 28-lead 0.3" SOIC package and a
28-lead 0.6" PDIP package, and the AD7835 is available in a
44-lead MQFP package and a 44-lead PLCC package.
APPLICATIONS
Process control
Automatic test equipment
General-purpose instrumentation
GENERAL DESCRIPTION
The AD7834 and AD7835 contain four 14-bit DACs on one
monolithic chip. The AD7834 and AD7835 have output
voltages in the range ±8.192 V with a maximum span of 14 V.
The AD7834 is a serial input device. Data is loaded in 16-bit
format from the external serial bus, MSB first after two leading 0s,
FUNCTIONAL BLOCK DIAGRAMS
V
CC
V
DD
V
SS
V
REF
(–) V
REF
(+)
V
CC
V
DD
V
SS
V
REF
(–)A V
REF
(+)A DSGA
AD7834
PAEN
PA0
PA1
PA2
PA3
PA4
FSYNC
DIN
SCLK
SERIAL-TO-
PARALLEL
CONVERTER
CONTROL
LOGIC
AND
ADDRESS
DECODE
INPUT
REGISTER
1
DAC 1
LATCH
AD7835
DAC 1
×1
BYSHF
INPUT
REGISTER
1
14
INPUT
REGISTER
2
DAC 1
LATCH
DAC 1
×1
V
OUT
1
DB13
DB0
INPUT
BUFFER
V
OUT
1
INPUT
REGISTER
2
DAC 2
LATCH
DAC 2
×1
DAC 2
LATCH
DAC 2
×1
V
OUT
2
WR
CS
INPUT
REGISTER
3
INPUT
REGISTER
4
DAC 3
LATCH
DAC 3
V
OUT
2
INPUT
REGISTER
3
DAC 3
LATCH
DAC 3
×1
V
OUT
3
×1
DAC 4
LATCH
V
OUT
3
A0
A1
ADDRESS
DECODE
DAC 4
×1
INPUT
REGISTER
4
DAC 4
LATCH
DAC 4
×1
V
OUT
4
01006-001
A2
V
OUT
4
01006-002
CLR
AGND
DGND
LDAC
DSG
CLR
AGND
DGND
LDAC V
REF
(–)B V
REF
(+)B DSGB
Figure 1. AD7834
Figure 2. AD7835
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2003–2007 Analog Devices, Inc. All rights reserved.
AD7834/AD7835
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Performance Characteristics ................................................ 5
Timing Specifications .................................................................. 6
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ........................................... 11
Terminology .................................................................................... 13
Theory of Operation ...................................................................... 14
DAC Architecture....................................................................... 14
Data Loading—AD7834 Serial Input Device ......................... 14
Data Loading—AD7835 Parallel Loading Device ................. 14
Unipolar Configuration............................................................. 15
Bipolar Configuration................................................................ 16
Controlled Power-On of the Output Stage.................................. 17
Power-On with CLR Low, LDAC High ................................... 17
Power-On with LDAC Low, CLR High ................................... 17
Loading the DAC and Using the CLR Input .......................... 17
DSG Voltage Range .................................................................... 18
Power-On of the AD7834/AD7835.............................................. 19
Microprocessor Interfacing........................................................... 20
AD7834 to 80C51 Interface ...................................................... 20
AD7834 to 68HC11 Interface ................................................... 20
AD7834 to ADSP-2101 Interface ............................................. 20
AD7834 to DSP56000/DSP56001 Interface............................ 21
AD7834 to TMS32020/TMS320C25 Interface....................... 21
Interfacing the AD7835—16-Bit Interface.............................. 21
Interfacing the AD7835—8-Bit Interface................................ 22
Applications Information .............................................................. 23
Serial Interface to Multiple AD7834s ...................................... 23
Opto-Isolated Interface ............................................................. 23
Automated Test Equipment ...................................................... 23
Power Supply Bypassing and Grounding................................ 24
Outline Dimensions ....................................................................... 25
Ordering Guide .......................................................................... 27
REVISION HISTORY
8/07—Rev.
C to Rev. D
Changes to Table 5 ........................................................................... 7
Added Table 6.................................................................................... 7
Changes to Table 8............................................................................ 9
Updated Outline Dimensions ....................................................... 25
Changes to Ordering Guide .......................................................... 27
7/05—Rev. B to Rev. C
Updated Format..................................................................Universal
Changes to Figure 40...................................................................... 25
Changes to Ordering Guide .......................................................... 27
7/03—Rev. A to Rev. B
Revision 0: Initial Version
Rev. D | Page 2 of 28
AD7834/AD7835
SPECIFICATIONS
V
CC
= 5 V ± 5%; V
DD
= 15 V ± 5%; V
SS
= −15 V ± 5%; AGND = DGND = 0 V; T
A 1
= T
MIN
to T
MAX
, unless otherwise noted.
Table 1.
Parameter
ACCURACY
Resolution
Relative Accuracy
Differential Nonlinearity
Full-Scale Error
T
MIN
to T
MAX
Zero-Scale Error
Gain Error
Gain Temperature
Coefficient
2
DC Crosstalk
REFERENCE INPUTS
DC Input Resistance
Input Current
V
REF
(+) Range
V
REF
(−) Range
V
REF
(+) − V
REF
(−)
DEVICE SENSE GROUND INPUTS
Input Current
DIGITAL INPUTS
V
INH
, Input High Voltage
V
INL
, Input Low Voltage
I
INH
, Input Current
C
IN
, Input Capacitance
POWER REQUIREMENTS
V
CC
V
DD
V
SS
Power Supply Sensitivity
ΔFull Scale/ΔV
DD
ΔFull Scale/ΔV
SS
I
CC
±2
2.4
0.8
±10
10
5.0
15.0
−15.0
110
100
0.2
3
6
13
15
13
±2
2.4
0.8
±10
10
5.0
15.0
−15.0
110
100
0.2
3
6
13
15
13
±2
2.4
0.8
±10
10
5.0
15.0
−15.0
110
100
0.5
3
6
15
15
15
μA max
V min
V max
μA max
pF max
V nom
V nom
V nom
dB typ
dB typ
mA max
mA max
mA max
mA max
mA max
mA max
±5% for specified performance.
±5% for specified performance.
±5% for specified performance.
Per input. V
DSG
= −2 V to +2 V.
2
A
14
±2
±0.9
±5
±4
±0.5
4
20
50
30
±1
0/8.192
−8.192/0
5/14
B
14
±1
±0.9
±5
±4
±0.5
4
20
50
30
±1
0/8.192
−8.192/0
7/14
S
14
±2
±0.9
±8
±5
±0.5
4
20
50
30
±1
0/8.192
−8.192/0
5/14
Unit
Bits
LSB max
LSB max
mV max
mV max
mV typ
ppm FSR/°C typ
ppm FSR/°C max
μV max
MΩ typ
μA max
V min/max
V min/max
V min/max
Test Conditions/Comments
Guaranteed monotonic over temperature.
V
REF
(+) = +7 V, V
REF
(−) = −7 V.
V
REF
(+) = +7 V, V
REF
(−) = −7 V.
V
REF
(+) = +7 V, V
REF
(−) = −7 V.
See the Terminology section. R
L
= 10 kΩ.
Per input.
For specified performance. Can go as low as
0 V, but performance is not guaranteed.
I
DD
I
SS
1
2
V
INH
= V
CC
, V
INL
= DGND.
AD7834: V
INH
= 2.4 V min, V
INL
= 0.8 V max.
AD7835: V
INH
= 2.4 V min, V
INL
= 0.8 V max.
AD7834: outputs unloaded.
AD7835: outputs unloaded.
Outputs unloaded.
Temperature range for A, B, and C versions is
−40°C
to +85°C.
Guaranteed by design.
Rev. D | Page 3 of 28
AD7834/AD7835
V
CC
= 5 V ± 5%; V
DD
= 12 V ± 5%; V
SS
= −12 V ± 5%; AGND = DGND = 0 V; T
A
1
= T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter
ACCURACY
Resolution
Relative Accuracy
Differential Nonlinearity
Full-Scale Error
T
MIN
to T
MAX
Zero-Scale Error
Gain Error
Gain Temperature Coefficient
2
DC Crosstalk
2
REFERENCE INPUTS
DC Input Resistance
Input Current
V
REF
(+) Range
V
REF
(−) Range
V
REF
(+) − V
REF
(−)
DEVICE SENSE GROUND INPUTS
Input Current
DIGITAL INPUTS
V
INH
, Input High Voltage
V
INL
, Input Low Voltage
I
INH
, Input Current
C
IN
, Input Capacitance
POWER REQUIREMENTS
V
CC
V
DD
V
SS
Power Supply Sensitivity
ΔFull Scale/ΔV
DD
ΔFull Scale/ΔV
SS
I
CC
±2
2.4
0.8
±10
10
5.0
15.0
−15.0
110
100
0.2
3
6
13
15
13
±2
2.4
0.8
±10
10
5.0
15.0
−15.0
110
100
0.2
3
6
13
15
13
±2
2.4
0.8
±10
10
5.0
15.0
−15.0
110
100
0.5
3
6
15
15
15
μA max
V min
V max
μA max
pF max
V nom
V nom
V nom
dB typ
dB typ
mA max
mA max
mA max
mA max
mA max
mA max
±5% for specified performance.
±5% for specified performance.
±5% for specified performance.
Per input. V
DSG
= −2 V to +2 V.
A
14
±2
±0.9
±5
±4
±0.5
4
20
50
30
±1
0/8.192
−5/0
5/13.192
B
14
±1
±0.9
±5
±4
±0.5
4
20
50
30
±1
0/8.192
−5/0
7/13.192
S
14
±2
±0.9
±8
±5
±0.5
4
20
50
30
±1
0/8.192
−5/0
5/13.192
Unit
Bits
LSB max
LSB max
mV max
mV max
mV typ
ppm FSR/°C typ
ppm FSR/°C max
μV max
MΩ typ
μA max
V min/max
V min/max
V min/max
Test Conditions/Comments
Guaranteed monotonic over temperature.
V
REF
(+) = +5 V, V
REF
(−) = –5 V.
V
REF
(+) = +5 V, V
REF
(−) = −5 V.
V
REF
(+) = +5 V, V
REF
(−) = −5 V.
See the Terminology section. R
L
= 10 kΩ.
Per input.
For specified performance. Can go as low as
0 V, but performance is not guaranteed.
I
DD
I
SS
1
2
V
INH
= V
CC
, V
INL
= DGND.
AD7834: V
INH
= 2.4 V min, V
INL
= 0.8 V max.
AD7835: V
INH
= 2.4 V min, V
INL
= 0.8 V max.
AD7834: outputs unloaded.
AD7835: outputs unloaded.
Outputs unloaded.
Temperature range for A, B, and C versions is
−40°C
to +85°C.
Guaranteed by design.
Rev. D | Page 4 of 28
AD7834/AD7835
AC PERFORMANCE CHARACTERISTICS
These characteristics are included for design guidance and are not subject to production testing.
Table 3.
Parameter
DYNAMIC PERFORMANCE
Output Voltage Settling Time
Digital-to-Analog Glitch Impulse
DC Output Impedance
Channel-to-Channel Isolation
DAC-to-DAC Crosstalk
Digital Crosstalk
Digital Feedthrough—AD7834
Digital Feedthrough—AD7835
Output Noise Spectral Density at 1 kHz
A
10
120
0.5
100
25
3
0.2
1.0
40
B
10
120
0.5
100
25
3
0.2
1.0
40
S
10
120
0.5
100
25
3
0.2
1.0
40
Unit (typ)
μs
nV-s
Ω
dB
nV-s
nV-s
nV-s
nV-s
nV/√Hz
Test Conditions/Comments
Full-scale change to ±1/2 LSB. DAC latch contents
alternately loaded with all 0s and all 1s.
Measured with V
REF
(+) = V
REF
(−) = 0 V. DAC latch
alternately loaded with all 0s and all 1s.
See the Terminology section.
See the Terminology section; applies to the AD7835 only.
See the Terminology section.
Feedthrough to DAC output under test due to change in
digital input code to another converter.
Effect of input bus activity on DAC output under test.
All 1s loaded to DAC. V
REF
(+) = V
REF
(−) = 0 V.
Rev. D | Page 5 of 28
京公网安备 11010802033920号
EEWORLD
