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74AHCT74PW/T3

Description
IC AHCT/VHCT/VT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, 4.40 MM, PLASTIC, MO-153, SOT-402-1, TSSOP-14, FF/Latch
Categorylogic    logic   
File Size103KB,18 Pages
ManufacturerNXP
Websitehttps://www.nxp.com
Environmental Compliance
Download Datasheet Parametric Compare View All

74AHCT74PW/T3 Overview

IC AHCT/VHCT/VT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, 4.40 MM, PLASTIC, MO-153, SOT-402-1, TSSOP-14, FF/Latch

74AHCT74PW/T3 Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerNXP
Parts packaging codeTSSOP
package instructionTSSOP,
Contacts14
Reach Compliance Codeunknown
seriesAHCT/VHCT/VT
JESD-30 codeR-PDSO-G14
JESD-609 codee4
length5 mm
Logic integrated circuit typeD FLIP-FLOP
Humidity sensitivity level1
Number of digits1
Number of functions2
Number of terminals14
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
Output polarityCOMPLEMENTARY
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
propagation delay (tpd)12 ns
Certification statusNot Qualified
Maximum seat height1.1 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal surfaceNICKEL PALLADIUM GOLD
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
Trigger typePOSITIVE EDGE
width4.4 mm
minfmax80 MHz
Base Number Matches1
74AHC74; 74AHCT74
Dual D-type flip-flop with set and reset; positive-edge trigger
Rev. 05 — 9 June 2008
Product data sheet
1. General description
The 74AHC74; 74AHCT74 is a high-speed Si-gate CMOS device and is pin compatible
with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
No. 7-A.
The 74AHC74; 74AHCT74 is a dual positive-edge triggered, D-type flip-flop with individual
data inputs (D), clock inputs (CP), set inputs (SD) and reset inputs (RD). It also has
complementary outputs (Q and Q).
The set and reset are asynchronous active LOW inputs that operate independent of the
clock input. Information on the data input is transferred to the Q output on the LOW to
HIGH transition of the clock pulse. The data inputs must be stable one set-up time prior to
the LOW to HIGH clock transition for predictable operation.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock
rise and fall times.
2. Features
I
I
I
I
Balanced propagation delays
All inputs have Schmitt-trigger actions
Inputs accept voltages higher than V
CC
Input levels:
N
For 74AHC74: CMOS level
N
For 74AHCT74: TTL level
I
ESD protection:
N
HBM EIA/JESD22-A114E exceeds 2000 V
N
MM EIA/JESD22-A115-A exceeds 200 V
N
CDM EIA/JESD22-C101C exceeds 1000 V
I
Multiple package options
I
Specified from
−40 °C
to +85
°C
and from
−40 °C
to +125
°C

74AHCT74PW/T3 Related Products

74AHCT74PW/T3 74AHCT74PW-T 74AHCT74D-T
Description IC AHCT/VHCT/VT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, 4.40 MM, PLASTIC, MO-153, SOT-402-1, TSSOP-14, FF/Latch Trigger dual D-type flipflop Trigger dual D-type flipflop
Is it Rohs certified? conform to conform to conform to
Maker NXP NXP NXP
Parts packaging code TSSOP TSSOP SOIC
package instruction TSSOP, TSSOP, TSSOP14,.25 3.90 MM, PLASTIC, MS-012, SOT-108-1, SO-14
Contacts 14 14 14
Reach Compliance Code unknown unknow unknow
series AHCT/VHCT/VT AHCT/VHCT AHCT/VHCT
JESD-30 code R-PDSO-G14 R-PDSO-G14 R-PDSO-G14
JESD-609 code e4 e4 e4
length 5 mm 5 mm 8.65 mm
Logic integrated circuit type D FLIP-FLOP D FLIP-FLOP D FLIP-FLOP
Humidity sensitivity level 1 1 1
Number of digits 1 1 1
Number of functions 2 2 2
Number of terminals 14 14 14
Maximum operating temperature 125 °C 125 °C 125 °C
Minimum operating temperature -40 °C -40 °C -40 °C
Output polarity COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TSSOP TSSOP SOP
Package shape RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE
Peak Reflow Temperature (Celsius) 260 260 260
propagation delay (tpd) 12 ns 11 ns 11 ns
Certification status Not Qualified Not Qualified Not Qualified
Maximum seat height 1.1 mm 1.1 mm 1.75 mm
Maximum supply voltage (Vsup) 5.5 V 5.5 V 5.5 V
Minimum supply voltage (Vsup) 4.5 V 4.5 V 4.5 V
Nominal supply voltage (Vsup) 5 V 5 V 5 V
surface mount YES YES YES
technology CMOS CMOS CMOS
Temperature level AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE
Terminal surface NICKEL PALLADIUM GOLD Nickel/Palladium/Gold (Ni/Pd/Au) NICKEL PALLADIUM GOLD
Terminal form GULL WING GULL WING GULL WING
Terminal pitch 0.65 mm 0.65 mm 1.27 mm
Terminal location DUAL DUAL DUAL
Maximum time at peak reflow temperature 30 30 30
Trigger type POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE
width 4.4 mm 4.4 mm 3.9 mm
minfmax 80 MHz 80 MHz 80 MHz
Base Number Matches 1 1 1
Source Url Status Check Date - 2013-06-14 00:00:00 2013-06-14 00:00:00
Load capacitance (CL) - 50 pF 50 pF
Maximum Frequency@Nom-Su - 65000000 Hz 65000000 Hz
MaximumI(ol) - 0.008 A 0.008 A
Output characteristics - 3-STATE 3-STATE
Encapsulate equivalent code - TSSOP14,.25 SOP14,.25
method of packing - TAPE AND REEL TAPE AND REEL
power supply - 5 V 5 V
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