, unless otherwise noted.) Specifications in ( ) apply to the AD7858L.
Parameter
DYNAMIC PERFORMANCE
Signal to Noise + Distortion Ratio
3
(SNR)
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise
Intermodulation Distortion (IMD)
Second Order Terms
Third Order Terms
Channel-to-Channel Isolation
DC ACCURACY
Resolution
Integral Nonlinearity
A Version
1
B Version
1
70
–78
–78
–78
–78
–90
12
±
1
±
1
(± 1)
±
1
±
1
±
5
±
2.5
(± 3)
(± 1.5)
1.5
±
4
±
1.5
1
0 to V
REF
±
1
20
2.3/V
DD
150
2.3/2.7
20
2.4
2.1
0.8
0.6
±
10
10
71
–78
–78
–80
–80
–90
12
±
1
±
0.5
(± 1)
±
1
±
1
±
5
±
2.5
(± 3)
(± 1.5)
1.5
±
4
±
1.5
1
0 to V
REF
±
1
20
2.3/V
DD
150
2.3/2.7
20
2.4
2.1
0.8
0.6
±
10
10
Units
dB min
dB max
dB max
dB typ
dB typ
dB typ
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
LSB typ
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
Volts
µA
max
pF typ
V min/max
kΩ typ
V min/max
ppm/°C typ
V min
V min
V max
V max
µA
max
pF max
Functional from 1.2 V
Test Conditions/Comments
Typically SNR is 72 dB
V
IN
= 10 kHz Sine Wave, f
SAMPLE
= 200 kHz (100 kHz)
V
IN
= 10 kHz Sine Wave, f
SAMPLE
= 200 kHz (100 kHz)
V
IN
= 10 kHz Sine Wave, f
SAMPLE
= 200 kHz (100 kHz)
fa = 9.983 kHz, fb = 10.05 kHz, f
SAMPLE
= 200 kHz (100 kHz)
fa = 9.983 kHz, fb = 10.05 kHz, f
SAMPLE
= 200 kHz (100 kHz)
V
IN
= 25 kHz
Any Channel
2.5 V External Reference V
DD
= 3 V, V
DD
= 5 V (B Grade Only)
5 V External Reference V
DD
= 5 V
(L Version, 5 V External Reference, V
DD
= 5 V)
(L Version)
Guaranteed No Missed Codes to 12 Bits. 2.5 V External
Reference V
DD
= 3 V, 5 V External Reference, V
DD
= 5 V
Typically
±
2 LSBs
5 V External Reference, V
DD
= 5 V
(L Version)
(L Version, 5 V External Reference, V
DD
= 5 V)
CLKIN
SAMPLE
Differential Nonlinearity
Total Unadjusted Error
Unipolar Offset Error
Unipolar Offset Error Match
Positive Full-Scale Error
Positive Full-Scale Error Match
ANALOG INPUT
Input Voltage Ranges
Leakage Current
Input Capacitance
REFERENCE INPUT/OUTPUT
REF
IN
Input Voltage Range
Input Impedance
REF
OUT
Output Voltage
REF
OUT
Tempco
LOGIC INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
Input Capacitance, C
IN4
LOGIC OUTPUTS
Output High Voltage, V
OH
5 V External Reference, V
DD
= 5 V
i.e., AIN(+) – AIN(–) = 0 to V
REF
, AIN(–) can be biased
up but AIN(+) cannot go below AIN(–)
AV
DD
= DV
DD
= 4.5 V to 5.5 V
AV
DD
= DV
DD
= 3.0 V to 3.6 V
AV
DD
= DV
DD
= 4.5 V to 5.5 V
AV
DD
= DV
DD
= 3.0 V to 3.6 V
Typically 10 nA, V
IN
= 0 V or V
DD
Output Low Voltage, V
OL
Floating-State Leakage Current
Floating-State Output Capacitance
4
Output Coding
CONVERSION RATE
Conversion Time
Track/Hold Acquisition Time
4
4
2.4
2.4
0.4
0.4
±
10
±
10
10
10
Straight (Natural) Binary
4.6 (18)
0.4 (1)
4.6
(10)
0.4 (1)
V min
V min
V max
µA
max
pF max
I
SOURCE
= 200
µA
AV
DD
= DV
DD
= 4.5 V to 5.5 V
AV
DD
= DV
DD
= 3.0 V to 3.6 V
I
SINK
= 0.8 mA
µs
max
µs
max
µs
min
(L Versions Only, –40°C to +85°C, 1 MHz CLKIN)
(L Versions Only, 0°C to +70°C, 1.8 MHz CLKIN)
(L Versions Only)
–2–
REV. B
AD7858/AD7858L
Parameter
DYNAMIC PERFORMANCE
AV
DD,
DV
DD
I
DD
Normal Mode
5
Sleep Mode
6
With External Clock On
A Version
1
+3.0/+5.5
6 (1.9)
5.5 (1.9)
10
400
With External Clock Off
5
B Version
1
+3.0/+5.5
6 (1.9)
5.5 (1.9)
10
400
5
Units
V min/max
mA max
mA max
µA
typ
µA
typ
µA
max
µA
typ
mW max
mW max
µW
typ
µW
typ
µW
max
µW
max
V max/min
V max/min
AV
DD
= DV
DD
= 4.5 V to 5.5 V. Typically 4.5 mA (1.5)
AV
DD
= DV
DD
= 3.0 V to 3.6 V. Typically 4.0 mA (1.5 mA)
Full Power-Down. Power Management Bits in Control
Register Set as PMGT1 = 1, PMGT0 = 0
Partial Power-Down. Power Management Bits in
Control Register Set as PMGT1 = 1, PMGT0 = 1
Typically 1
µA.
Full Power-Down. Power Management Bits
in Control
Register Set as PMGT1 = 1, PMGT0 = 0
Partial Power-Down. Power Management Bits in Control
Register Set as PMGT1 = 1, PMGT0 = 1
V
DD
= 5.5 V. Typically 25 mW (8);
SLEEP
= V
DD
V
DD
= 3.6 V. Typically 15 mW (5.4);
SLEEP
= V
DD
V
DD
= 5.5 V.
SLEEP
= 0 V
V
DD
= 3.6 V.
SLEEP
= 0 V
V
DD
= 5.5 V. Typically 5.5
µW;
SLEEP
= 0 V
V
DD
= 3.6 V. Typically 3.6
µW;
SLEEP
= 0 V
Allowable Offset Voltage Span for Calibration
Allowable Full-Scale Voltage Span for Calibration
Test Conditions/Comments
200
Normal-Mode Power Dissipation
Sleep Mode Power Dissipation
With External Clock On
With External Clock Off
SYSTEM CALIBRATION
Offset Calibration Span
7
Gain Calibration Span
7
33 (10.5)
20 (6.85)
55
36
27.5
18
200
33 (10.5)
20 (6.85)
55
36
27.5
18
+0.05
×
V
REF
/–0.05
×
V
REF
+1.025
×
V
REF
/–0.975
×
V
REF
NOTES
1
Temperature ranges as follows: A, B Versions: –40°C to +85°C. For L Versions, A and B Versions f
CLKIN
= 1 MHz over –40°C to +85°C temperature range,
B Version f
CLKIN
= 1.8 MHz over 0°C to +70°C temperature range.
2
Specifications apply after calibration.
3
SNR calculation includes distortion and noise components.
4
Sample tested @ +25°C to ensure compliance.
5
All digital inputs @ DGND except for
CONVST, SLEEP, CAL,
and
SYNC
@ DV
DD
. No load on the digital outputs. Analog inputs @ AGND.
6
CLKIN @ DGND when external clock off. All digital inputs @ DGND except for
CONVST, SLEEP, CAL,
and
SYNC
@ DV
DD
. No load on the digital
outputs. Analog inputs @ AGND.
7
The Offset and Gain Calibration Spans are defined as the range of offset and gain errors that the AD7858/AD7858L can calibrate. Note also that these are voltage
spans and are not absolute voltages ( i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–)
±
0.05
×
V
REF
, and the allowable system full-scale voltage applied between AIN(+) and AIN(–) for the system full-scale voltage error to be adjusted out will be
V
REF
±
0.025
×
V
REF
). This is explained in more detail in the Calibration section of the data sheet.
Specifications subject to change without notice.
REV. B
–3–
AD7858/AD7858L
TIMING
Parameter
f
CLKIN2
DD
DD
CLKIN
1
T = T to T , unless otherwise noted)
SPECIFICATIONS
A MIN MAX
(AV = DV = +3.0 V to +5.5 V; f
= 4 MHz for AD7858 and 1.8/1 MHz for AD7858L;
Limit at T
MIN
, T
MAX
(A, B Versions)
5V
3V
500
4
1.8
1
4
100
50
4.6
10 (18)
–0.4 t
SCLK
0.4 t
SCLK
50
50
75
40
20
0.4 t
SCLK
0.4 t
SCLK
30
30/0.4 t
SCLK
50
90
50
2.5 t
CLKIN
2.5 t
CLKIN
31.25
27.78
3.47
500
4
1.8
1
4
100
90
4.6
10 (18)
–0.4 t
SCLK
0.4 t
SCLK
90
90
115
60
30
0.4 t
SCLK
0.4 t
SCLK
50
50/0.4 t
SCLK
50
130
90
2.5 t
CLKIN
2.5 t
CLKIN
31.25
27.78
3.47
Units
kHz min
MHz max
MHz max
MHz max
MHz max
ns min
ns max
µs
max
µs
max
ns min
ns min/max
ns max
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns min/max
ns max
ns max
ns max
ns max
ns max
ms typ
ms typ
ms typ
Description
Master Clock Frequency
L Version, 0°C to +70°C, B Grade Only
L Version, –40°C to +85°C
CONVST
Pulsewidth
CONVST↓
to BUSY↑ Propagation Delay
Conversion Time = 18 t
CLKIN
L Version 1.8 (1) MHz CLKIN. Conversion Time = 18 t
CLKIN
SYNC↓
to SCLK↓ Setup Time (Noncontinuous SCLK Input)
SYNC↓
to SCLK↓ Setup Time (Continuous SCLK Input)
Delay from
SYNC↓
Until DOUT Three-State Disabled
Delay from
SYNC↓
Until DIN Three-State Disabled
Data Access Time After SCLK↓
Data Setup Time Prior to SCLK↑
Data Valid to SCLK Hold Time
SCLK High Pulsewidth
SCLK Low Pulsewidth
SCLK↑ to
SYNC↑
Hold Time (Noncontinuous SCLK)
(Continuous SCLK)
Delay from
SYNC↑
Until DOUT Three-State Enabled
Delay from SCLK↑ to DIN Being Configured as Output
Delay from SCLK↑ to DIN Being Configured as Input
CAL↑
to BUSY↑ Delay
CONVST↓
to BUSY↑ Delay in Calibration Sequence
Full Self-Calibration Time, Master Clock Dependent
(125013 t
CLKIN
)
Internal DAC Plus System Full-Scale Calibration Time, Master
Clock Dependent (111114 t
CLKIN
)
System Offset Calibration Time, Master Clock Dependent
(13899 t
CLKIN
)
f
SCLK
t
1 3
t
2
t
CONVERT
t
3
t
4 4
t
5 4
t
6 4
t
7
t
8
t
9
t
10
t
11
t
125
t
13
t
146
t
15
t
16
t
CAL7
t
CAL17
t
CAL27
NOTES
1
Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
See Table XI and timing diagrams for different interface modes and Calibration.
2
Mark/Space ratio for the master clock input is 40/60 to 60/40.
3
The
CONVST
pulsewidth will apply here only for normal operation. When the part is in power-down mode, a different
CONVST
pulsewidth will apply
(see Power-Down section).
4
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
5
t
12
is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time, t
12
, quoted in the timing characteristics is the true bus
relinquish time of the part and is independent of the bus loading.
6
t
14
is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the Timing Characteristics is the
true delay of the part in turning off the output drivers and configuring the DIN line as an input. Once this time has elapsed the user can drive the DIN line
knowing that a bus conflict will not occur.
7
The typical time specified for the calibration times is for a master clock of 4 MHz. For the L version the calibration times will be longer than those quoted here due to
the 1.8/1 MHz master clock.
Specifications subject to change without notice.
–4–
REV. B
AD7858/AD7858L
TYPICAL TIMING DIAGRAMS
Figures 2 and 3 show typical read and write timing diagrams for
serial Interface Mode 2. The reading and writing occurs after
conversion in Figure 2, and during conversion in Figure 3. To
attain the maximum sample rate of 100 kHz (AD7858L) or
200 kHz (AD7858), reading and writing must be performed
during conversion as in Figure 3. At least 400 ns acquisition
time must be allowed (the time from the falling edge of BUSY
to the next rising edge of
CONVST)
before the next conversion
begins to ensure that the part is settled to the 12-bit level. If the
user does not want to provide the
CONVST
signal, the conver-
sion can be initiated in software by writing to the control register.
1.6mA
I
OL
TO
OUTPUT
PIN
+2.1V
C
L
100pF
200 A
I
OH
Figure 1. Load Circuit for Digital Output Timing
Specifications
t
CONVERT
= 4.6 s MAX, 10 s MAX FOR L VERSION
t
1
= 100ns MIN,
t
4
= 50/90ns MAX 5V/3V,
t
7
= 40/60ns MIN 5V/3V
t
1
CONVST
(I/P)
t
2
BUSY (O/P)
t
CONVERT
SYNC
(I/P)
t
3
SCLK (I/P)
1
5
t
9
6
16
t
11
t
10
t
12
DB0
THREE-
STATE
t
4
DOUT (O/P)
THREE-STATE
t
6
DB15
t
6
DB11
t
7
DIN (I/P)
DB15
t
8
DB11
DB0
Figure 2. AD7858/AD7858L Timing Diagram for Interface Mode 2 (Reading/Writing After Conversion)
t
CONVERT
= 4.6 s MAX, 10 s MAX FOR L VERSION
t
1
= 100ns MIN,
t
4
= 50/90ns MAX 5V/3V,
t
7
= 40/60ns MIN 5V/3V
t
1
CONVST
(I/P)
t
2
BUSY (O/P)
t
CONVERT
SYNC
(I/P)
t
3
SCLK (I/P)
1
5
t
9
6
16
t
11
t
10
t
12
DB0
THREE-
STATE
t
4
DOUT (O/P)
THREE-STATE
t
6
DB15
t
6
DB11
t
7
DIN (I/P)
DB15
t
8
DB11
DB0
Figure 3. AD7858/AD7858L Timing Diagram for Interface Mode 2 (Reading/Writing During Conversion)
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