= 4 MHz (for L Version: 1.8 MHz (0 C to +70 C) and
C));
=
kHz (AD7859) 100
DD
DD
IN
OUT
CLKIN
SAMPLE
(AD7859L);
SLEEP
= Logic High; T
A
= T
MIN
to T
MAX
, unless otherwise noted.) Specifications in () apply to the AD7859L.
Parameter
DYNAMIC PERFORMANCE
Signal to Noise + Distortion Ratio
3
(SNR)
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise
Intermodulation Distortion (IMD)
Second Order Terms
Third Order Terms
Channel-to-Channel Isolation
DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Unipolar Offset Error
Unipolar Offset Error Match
Positive Full-Scale Error
Negative Full-Scale Error
Full-Scale Error Match
Bipolar Zero Error
Bipolar Zero Error Match
ANALOG INPUT
Input Voltage Ranges
A Version
1
B Version
1
Units
Test Conditions/Comments
70
71
dB min
–78
–78
–78
–78
dB max
dB max
Typically SNR is 72 dB
V
IN
= 10 kHz Sine Wave, f
SAMPLE
= 200 kHz
(for L Version: f
SAMPLE
= 100 kHz @ f
CLKIN
= 2 MHz)
V
IN
= 10 kHz Sine Wave, f
SAMPLE
= 200 kHz
(for L Version: f
SAMPLE
= 100 kHz @ f
CLKIN
= 2 MHz)
V
IN
= 10 kHz Sine Wave, f
SAMPLE
= 200 kHz
(for L Version: f
SAMPLE
= 100 kHz @ f
CLKIN
= 2 MHz)
fa = 9.983 kHz, fb = 10.05 kHz, f
SAMPLE
= 200 kHz
(for L Version: f
SAMPLE
= 100 kHz @ f
CLKIN
= 2 MHz)
fa = 9.983 kHz, fb = 10.05 kHz, f
SAMPLE
= 200 kHz
(for L Version: f
SAMPLE
= 100 kHz @ f
CLKIN
= 2 MHz)
V
IN
= 25 kHz
–78
–78
–80
–78
–78
–80
dB typ
dB typ
dB typ
12
±
1
±
1
±
5
±
2
2(3)
±
5
±
2
±
2
1
±
1
2
12
±
0.5
±
1
±
5
±
2
2
±
5
±
2
±
2
1
±
1
2
Bits
LSB max
LSB max
LSB max
LSB typ
LSB max
LSB max
LSB typ
LSB max
LSB max
LSB typ
LSB typ
5 V Reference V
DD
= 5 V
Guaranteed No Missed Codes to 12 Bits
0 to V
REF
±
V
REF
/2
±
1
20
0 to V
REF
±
V
REF
/2
±
1
20
Volts
Volts
i.e., AIN(+) – AIN(–) = 0 to V
REF
, AIN(–) Can Be
Biased Up But AIN(+) Cannot Go Below AIN(–)
i.e., AIN(+) – AIN(–) = –V
REF
/2 to +V
REF
/2, AIN(–)
Should Be Biased to +V
REF
/2 and AIN(+) Can Go
Below AIN(–) But Cannot Go Below 0 V
Leakage Current
Input Capacitance
REFERENCE INPUT/OUTPUT
REF
IN
Input Voltage Range
Input Impedance
REF
OUT
Output Voltage
REF
OUT
Tempco
LOGIC INPUTS
Input High Voltage, V
INH
CAL
Pin
Input Low Voltage, V
INL
Input Current, I
IN
Input Capacitance, C
IN4
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
Floating State Leakage Current
Floating-State Output Capacitance
4
Output Coding
µA
max
pF typ
2.3/V
DD
150
2.3/2.7
20
2.3/V
DD
150
2.3/2.7
20
V min/max
kΩ typ
V min/max
ppm/°C typ
Functional from 1.2 V
2.4
2.1
3
2.4
0.8
0.6
±
10
10
2.4
2.1
3
2.4
0.8
0.6
±
10
10
V min
V min
V min
V min
V max
V max
µA
max
pF max
AV
DD
= DV
DD
= 4.5 V to 5.5 V
AV
DD
= DV
DD
= 3.0 V to 3.6 V
AV
DD
= DV
DD
= 4.5 V to 5.5 V
AV
DD
= DV
DD
= 3.0 V to 3.6 V
AV
DD
= DV
DD
= 4.5 V to 5.5 V
AV
DD
= DV
DD
= 3.0 V to 3.6 V
Typically 10 nA, V
IN
= 0 V or V
DD
4
2.4
0.4
±
10
10
4
V min
2.4
V min
0.4
V max
±
10
µA
max
10
pF max
Straight (Natural) Binary
2s Complement
AV
DD
= DV
DD
= 4.5 V to 5.5 V
AV
DD
= DV
DD
= 3.0 V to 3.6 V
I
SINK
= 1.6 mA
Unipolar Input Range
Bipolar Input Range
–2–
REV. A
AD7859/AD7859L
Parameter
CONVERSION RATE
Conversion Time
Track/Hold Acquisition Time
A Version
1
B Version
1
Units
µs
max
µs
min
Test Conditions/Comments
t
CLKIN
×
18
(L Versions Only, 0°C to +70°C, 1.8 MHz CLKIN)
(L Versions Only, –40°C to +85°C, 1.8 MHz CLKIN)
4.5 (10)
0.5 (1)
4.5
0.5
POWER REQUIREMENTS
AV
DD,
DV
DD
I
DD
Normal Mode
5
Sleep Mode
6
With External Clock On
+3.0/+5.5
5.5 (1.95)
5.5 (1.95)
10
400
+3.0/+5.5
5.5
5.5
10
400
5
200
30 (10)
20 (6.5)
55
36
27.5
18
V min/max
mA max
mA max
µA
typ
µA
typ
µA
max
µA
typ
mW max
mW max
µW
typ
µW
typ
µW
max
µW
max
AV
DD
= DV
DD
= 4.5 V to 5.5 V. Typically 4.5 mA
AV
DD
= DV
DD
= 3.0 V to 3.6 V. Typically 4.0 mA
Full Power-Down. Power Management Bits in Control
Register Set as PMGT1 = 1, PMGT0 = 0.
Partial Power-Down. Power Management Bits in
Control Register Set as PMGT1 = 1, PMGT0 = 1.
Typically 1
µA.
Full Power-Down. Power Management
Bits in Control Register Set as PMGT1 = 1, PMGT0 = 0.
Partial Power-Down. Power Management Bits in
Control Register Set as PMGT1 = 1, PMGT0 = 1.
V
DD
= 5.5 V: Typically 25 mW (8);
SLEEP
= V
DD
V
DD
= 3.6 V: Typically 15 mW (5.4);
SLEEP
= V
DD
V
DD
= 5.5 V;
SLEEP
= 0 V
V
DD
= 3.6 V;
SLEEP
= 0 V
V
DD
= 5.5 V: Typically 5.5
µW;
SLEEP
= 0 V
V
DD
= 3.6 V: Typically 3.6
µW;
SLEEP
= 0 V
Allowable Offset Voltage Span for Calibration
Allowable Full-Scale Voltage Span for Calibration
With External Clock Off
5
200
Normal Mode Power Dissipation
Sleep Mode Power Dissipation
With External Clock On
With External Clock Off
30 (10)
20 (6.5)
55
36
27.5
18
SYSTEM CALIBRATION
Offset Calibration Span
7
Gain Calibration Span
7
+0.05
×
V
REF
/–0.05
×
V
REF
V max/min
+1.025
×
V
REF
/–0.975
×
V
REF
V max/min
NOTES
1
Temperature range as follows: A, B Versions, –40°C to +85°C.
2
Specifications apply after calibration.
3
SNR calculation includes distortion and noise components.
4
Not production tested, guaranteed by characterization at initial product release.
5
All digital inputs @ DGND except for
CONVST, SLEEP, CAL,
and
SYNC
@ DV
DD
. No load on the digital outputs. Analog inputs @ AGND.
6
CLKIN @ DGND when external clock off. All digital inputs @ DGND except for
CONVST, SLEEP, CAL,
and
SYNC
@ DV
DD
. No load on the digital outputs.
Analog inputs @ AGND.
7
The offset and gain calibration spans are defined as the range of offset and gain errors that the AD7859/AD7859L can calibrate. Note also that these are voltage spans
and are not absolute voltages (i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–)
±
0.05
×
V
REF
,
and the allowable system full-scale voltage applied between AIN(+) and AIN(–) for the system full-scale voltage error to be adjusted out will be V
REF
±
0.025
×
V
REF
).
This is explained in more detail in the calibration section of the data sheet.
Specifications subject to change without notice.
REV. A
–3–
AD7859/AD7859L
TIMING SPECIFICATIONS
Parameter
f
CLKIN2
t
1
t
2
t
CONVERT
t
3
t
4
t
5
t
6
t
7
t
8 4
t
9 5
t
10
t
11
t
12
t
13
t
14
t
15
t
16
t
17
t
184
t
19
t
CAL6
t
CAL16
t
CAL26
3
1
(AV
DD
= DV
DD
= +3.0 V to +5.5 V; f
CLKIN
= 4 MHz for AD7859 and 1.8 MHz for AD7859L;
T
A
= T
MIN
to T
MAX
, unless otherwise noted)
5V
Limit at T
MIN
, T
MAX
(A, B Versions)
3V
500
4
1.8
100
90
4.5
10
15
5
0
0
55
50
5
40
70
0
5
0
0
70
10
5
1/2 t
CLKIN
2.5 t
CLKIN
31.25
27.78
3.47
Units
kHz min
MHz max
MHz max
ns min
ns max
µs
max
µs
max
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns max
ms typ
ms typ
ms typ
Description
Master Clock Frequency
L Version
CONVST
Pulse Width
CONVST
to BUSY
↑
Propagation Delay
Conversion Time = 18 t
CLKIN
L Version 1.8 MHz CLKIN. Conversion Time = 18 t
CLKIN
HBEN to RD Setup Time
HBEN to RD Hold Time
CS
to
RD
to Setup Time
CS
to
RD
Hold Time
RD
Pulse Width
Data Access Time After
RD
Bus Relinquish Time After
RD
Bus Relinquish Time After
RD
Minimum Time Between Reads
HBEN to
WR
Setup Time
HBEN to
WR
Hold Time
CS
to
WR
Setup Time
CS
to
WR
Hold Time
WR
Pulse Width
Data Setup Time Before WR
Data Hold Time After WR
New Data Valid Before Falling Edge of BUSY
CS
↑
to BUSY
↑
in Calibration Sequence
Full Self-Calibration Time, Master Clock Dependent (125013
t
CLKIN
)
Internal DAC Plus System Full-Scale Cal Time, Master Clock
Dependent (111124 t
CLKIN
)
System Offset Calibration Time, Master Clock Dependent
(13889 t
CLKIN
)
500
4
1.8
100
50
4.5
10
15
5
0
0
55
50
5
40
60
0
5
0
0
55
10
5
1/2 t
CLKIN
2.5 t
CLKIN
31.25
27.78
3.47
NOTES
1
Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
2
Mark/Space ratio for the master clock input is 40/60 to 60/40.
3
The
CONVST
pulse width will here only apply for normal operation. When the part is in power-down mode, a different
CONVST
pulse width will apply (see Power-
Down section).
4
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
5
t
9
is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
9
, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
6
The typical time specified for the calibration times is for a master clock of 4 MHz. For the L version the calibration times will be longer than those quoted here due to
the 1.8 MHz master clock.
Specifications subject to change without notice.
–4–
REV. A
AD7859/AD7859L
ABSOLUTE MAXIMUM RATINGS
1
1.6mA
I
OL
(T
A
= +25°C unless otherwise noted)
TO OUTPUT
PIN
50pF
+2.1V
200µA
I
OH
Figure 1. Load Circuit for Digital Output Timing
Specifications
ORDERING GUIDE
Model
Linearity
Error
(LSB)
1
Power
Dissipation Package
(mW)
Option
2
15
15
15
5.5
P-44A
S-44
S-44
S-44
AD7859AP
±
1
AD7859AS
±
1
AD7859BS
±
1/2
3
AD7859LAS
±
1
4
EVAL-AD7859CB
EVAL-CONTROL BOARD
5
NOTES
1
Linearity error refers to the integral linearity error.
2
P = PLCC; S = PQFP.
3
L signifies the low power version.
4
This can be used as a stand-alone evaluation board or in conjunction with the
EVAL-CONTROL BOARD for evaluation/demonstration purposes.
5
This board is a complete unit allowing a PC to control and communicate with
all Analog Devices, Inc. evaluation boards ending in the CB designators.
For more information on Analog Devices products and evaluation boards, visit
our World Wide Web home page at http://www.analog.com.
AV
DD
to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DV
DD
to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AV
DD
to DV
DD
. . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Analog Input Voltage to AGND . . . . –0.3 V to AV
DD
+ 0.3 V
Digital Input Voltage to DGND . . . . –0.3 V to DV
DD
+ 0.3 V
Digital Output Voltage to DGND . . . –0.3 V to DV
DD
+ 0.3 V
REF
IN
/REF
OUT
to AGND . . . . . . . . . –0.3 V to AV
DD
+ 0.3 V
Input Current to Any Pin Except Supplies
2
. . . . . . . .
±
10 mA
Operating Temperature Range
Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
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