Temperature ranges are as follows : A, B Versions: –40°C to +85°C, Y Version: –40°C to +105°C.
2
Performance measured through full channel (SHA and ADC).
3
See Terminology.
4
Total Harmonic Distortion and Peak Harmonic or Spurious Noise are specified at –83 dBs for the AD7865-2.
5
Measured between any two channels with the other two channels grounded.
6
Sample tested @ +25°C to ensure compliance.
Specifications subject to change without notice.
REV. A
–3–
AD7865
TIMING CHARACTERISTICS
Parameter
t
CONV
t
ACQ
t
BUSY
t
WAKE-UP
—External
t
1
t
2
Read Operation
t
3
t
4
t
5
t
64
t
75
t
8
t
9
t
10
t
11
t
12
Write Operation
t
13
t
14
t
15
t
16
t
17
External Clock
t
18
V
REF3
1, 2
(V
DD
= +5 V
5%, AGND = DGND = 0 V, V
REF
= Internal, Clock = Internal; all specifications
T
MIN
to T
MAX
unless otherwise noted.)
Units
µs
max
µs
max
µs
max
µs
max
µs
max
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns min
ns min
ns max
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
Conversion Time, Internal Clock
Conversion Time, External Clock (5 MHz)
Acquisition Time
Selected Number of Channels Multiplied by t
CONV
STBY
Rising Edge to
CONVST
Rising Edge
CONVST
Pulsewidth
CONVST
Rising Edge to BUSY Rising Edge
CS
to
RD
Setup Time
CS
to
RD
Hold Time
Read Pulsewidth
Data Access Time After Falling Edge of
RD,
V
DRIVE
= 5 V
Data Access Time After Falling Edge of
RD,
V
DRIVE
= 3 V
Bus Relinquish Time After Rising Edge of
RD
Time Between Consecutive Reads
EOC
Pulsewidth
RD
Rising Edge to FRSTDATA Edge (Rising or Falling)
EOC
Falling Edge to FRSTDATA Falling Delay
EOC
to
RD
Delay
WR
Pulsewidth
CS
to
WR
Setup Time
WR
to
CS
Hold Time
Input Data Setup Time of Rising Edge of
WR
Input Data Hold Time
CONVST
Falling Edge to CLK Rising Edge
A, B, Y Versions
2.4
3.2
0.35
No. of Channels
×
(t
CONV
)
1
35
70
0
0
35
35
40
5
30
15
120
180
70
15
0
20
0
0
5
5
200
NOTES
1
Sample tested at +25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of +5 V) and timed from a voltage level of +1.6 V.
2
See Figures 6, 7 and 8.
3
Refer to the Standby Mode Operation section. The MAX specification of 1
µs
is valid when using a 0.1
µF
decoupling capacitor on the V
REF
pin.
4
Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
5
These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
Specifications subject to change without notice.
1.6mA
TO OUTPUT
PIN
50pF
400 A
+1.6V
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
–4–
REV. A
AD7865
ABSOLUTE MAXIMUM RATINGS*
(T
A
= +25°C unless otherwise noted)
V
DD
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
V
DD
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
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