531MB682M000DG datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Passive components> oscillator> 531MB682M000DG

531MB682M000DG: DescriptionLVPECL Output Clock Oscillator, 682MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

531MB682M000DG Overview

LVPECL Output Clock Oscillator, 682MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531MB682M000DG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
Reach Compliance Code	unknown
Other features	TRAY
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	20%
JESD-609 code	e4
Manufacturer's serial number	531
Installation features	SURFACE MOUNT
Nominal operating frequency	682 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVPECL
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)
Base Number Matches	1

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

Edifier 2.1 subwoofer circuit diagram produced by tda1521

Electric rice cooker circuit diagram Type I circuit diagram

Gas flow direction identification circuit

Constant voltage nickel-cadmium battery charger

Switch type oath generator circuit

Computer motherboard circuit diagram 810 2_21

MicroBlaze SOPC Design--Introduction: Learning SOPC requires a lot of time, including designing algorithms, languages, hardware and using TOOL. Currently, Altera's top recommendation is the NIOS II soft-core processor , and the recently l...; phdwong FPGA/CPLD

Show off the gift I received from EE today: Thank you EE, thank you MYLOVE...; dontium Talking

Communication between PC host computer and Delta PLC: Asking for advice: I have never touched PLC before, and now I have a project that requires me to use a PC host computer to control Delta PLC. I don't know how to start writing communication and contro...; taotao39329112 Embedded System

淺析android下如何通過jni監控wifi網絡連接、dhcpcd執行和power電源控制: [list] [*][font=simsun]轉載的：[url]http://blog.chinaunix.net/u1/38994/showart_1274854.html[/url][/font] [font=simsun]　　淺析android下如何通過jni監控wifi網絡連接、dhcpcd執行和power電源控制[/font] [font=simsun]　　===============...; Wince.Android Embedded System

How to move the program in flash to RAM: [i=s]This post was last edited by dontium on 2015-1-23 13:23[/i] 1. The specific question is how to move the program in flash to RAM during boot. How can I do that? It would be best if you could give ...; bangchuI Analogue and Mixed Signal

Has anyone used the at88sc series encryption chip?: Does anyone have the relevant driver code for this chip? I use I2C to read and write its MTZ area, but it's not right... Please help me, if you can provide useful information, I can open another threa...; ayangyzl Embedded System

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components