®
®
ADCDS-1403
14-Bit, 3 Megapixels/Second
Imaging Signal Processor
FEATURES
•
•
•
•
•
•
•
•
•
•
14-bit resolution
3MPPS throughput rate (14-bits)
Functionally complete
Very low noise
Excellent Signal-to-Noise ratio
Edge triggered
Small, 40-pin, TDIP package
Low power, 500mW typical
Low cost
Programmable Analog Bandwidth
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
INPUT/OUTPUT CONNECTIONS
FUNCTION
FINE GAIN ADJUST
OFFSET ADJUST
DIRECT INPUT
INVERTING INPUT
NON-INVERTING INPUT
+2.4V REF. OUTPUT
ANALOG GROUND
NO CONNECT
NO CONNECT
BIT 14 (LSB)
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
PIN
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
FUNCTION
NO CONNECT
+12V
–5VA
ANALOG GROUND
+5VA
ANALOG GROUND
+5VD
DIGITAL GROUND
DIGITAL GROUND
A1
A
NO CONNECT
NO CONNECT
DATA VALID
REFERENCE HOLD
START CONVERT
OUT-OF-RANGE
BIT 1 (MSB)
BIT 2
BIT 3
GENERAL DESCRIPTION
The ADCDS-1403 is an application-specific video signal
processor designed for electronic-imaging applications that
employ CCD's (charge coupled devices) as their
photodetector. The ADCDS-1403 incorporates a "user
configurable" input amplifier, a CDS (correlated double
sampler) and a sampling A/D converter in a single package,
providing the user with a complete, high performance, low-
cost, low-power, integrated solution.
The key to the ADCDS-1403's performance is a unique, high-
speed, high-accuracy CDS circuit, which eliminates the
effects of residual charge, charge injection and "kT/C" noise
on the CCD's output floating capacitor, producing a "valid
video" output signal. The ADCDS-1403 digitizes this resultant
"valid video" signal using a high-speed, low-noise sampling
A/D converter.
The ADCDS-1403 requires only the rising edge of start
convert pulse to initiate its conversion process. Additional
features of the ADCDS-1403 include gain adjust, offset
adjust, precision +2.4V reference, and a programmable
analog bandwidth function.
+12V
A
39
759
INVERTING INPUT 4
5239
–5V
A
38
+5V
A
36
+5V
D
34
INPUT AMPLIFIER
0.01µF
DIRECT INPUT 3
NON-INVERTING INPUT 5
5K
9
CORRELATED
DOUBLE
SAMPLER
25 START CONVERT
1 FINE GAIN ADJUST
23 BIT 1 (MSB)
SAMPLING
A/D
10 BIT 14 (LSB)
OFFSET ADJUST 2
REFERENCE HOLD 26
TIMING
AND
CONTROL
24 OUT-OF-RANGE
6
+2.4V REFERENCE OUTPUT
32, 33
DIGITAL GROUND
27
DATA VALID
30 31
AØ A1
7, 35, 37
ANALOG GROUND
Figure 1. ADCDS-1403 Functional Block Diagram
DATEL, Inc., Mansfield, MA 02048 (USA)
•
Tel: (508) 339-3000, (800) 233-2765 Fax: (508) 339-6356
•
Email: sales@datel.com
•
Internet: www.datel.com
®
®
ADCDS-1403
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
+12V Supply
(Pin 32)
–5V Supply
(Pin 38)
+5V Supply
(Pin 34, 36)
Digital Input
(Pin 25, 26, 30, 31)
Analog Input
(Pin 3,4,5)
Lead Temperature
(10 seconds)
MIN.
0
–6.5
–0.3
–0.3
–6
—
TYP.
—
—
—
—
—
—
MAX.
+14
+0.3
+6.5
Vdd+0.3V
+6
300
UNITS
Volts
Volts
Volts
Volts
Volts
°C
DYNAMIC PERFORMANCE
Reference Hold
Aquisition Time
Droop
@ +25°C
@ –55 to +125°C
Peak Harmonic (SFDR)
(CDD-IN, input on pin (3)
Input @ 98kHz)
@ +25 °C
@ 0 to +70°C
@ –55 to +125°C
Peak Harmonic (SFDR)
(Input on pin (5)
Input @ 98kHz)
@ +25 °C
@ 0 to +70°C
@ –55 to +125°C
Total Harmonic Distortion
(CDD-IN, input on pin (3)
Input @ 98kHz)
@ +25 °C
@ 0 to +70°C
@ –55 to +125°C
(Input on pin (5)
Input @ 98kHz)
@ +25 °C
@ 0 to +70°C
@ –55 to +125°C
Signal-to-Noise Ratio
Without Distortion
(CDD-IN, input on pin (3)
Input @ 98kHz)
@ +25 °C
@ 0 to +70°C
@ –55 to +125°C
(Input on pin (5)
Input @ 98kHz)
@ +25 °C
@ 0 to +70°C
@ –55 to +125°C
Signal-to-Noise Ratio
With Distortion
(CDD-IN, input on pin (3)
Input @ 98kHz)
@ +25 °C
@ 0 to +70°C
@ –55 to +125°C
(Input on pin (5)
Input @ 98kHz)
@ +25 °C
@ 0 to +70°C
@ –55 to +125°C
SIGNAL TIMING
Conversion Rate
–55 to +125°C
Conversion Time
Start Convert Pulse Width
POWER REQUIREMENTS
Power Supply Range
+12V Supply
+5V Supply
–5V Supply
+11.4
+4.75
–4.75
+12.0
+5.0
–5.0
+12.6
+5.25
–5.25
Volts
Volts
Volts
3
—
20
—
200
150
—
—
—
MHz
nsec
nsec
MIN.
100
—
—
TYP.
—
25
100
MAX.
—
—
—
UNITS
ns
mV/us
mV/us
FUNCTIONAL SPECIFICATIONS
Vcc=+12V, +Vdd=+5V, Vee=–5V, fin=98KHz, sample rate=3MHz.
T
he following specifications apply over the operating temperature range, under the following conditions:
ANALOG INPUT
Input Voltage Range
(externally configurable)
Input Resistance
Input Capacitance
DIGITAL INPUTS
Logic Levels
Logic 1
Logic 0
Logic Loading
Logic 1
Logic 0
DIGITAL OUTPUTS
Logic Levels
Logic 1 (IOH = .5ma)
Logic 1 (IOH = 50μa)
Logic 0 (IOL = 1.6ma)
Logic 0 (IOL = 50ua)
Internal Reference
Voltage
(Fine gain adjust pin (1) grounded)
+25°C
0 to 70°C
–55 to +125°C
External Current
STATIC PERFORMANCE
Differential Nonlinearity
(Histogram, 98kHz) +25°C
0 to 70°C
–55 to +125°C
Integral Nonlinearity
+25°C
0 to 70°C
–55 to +125°C
Guaranteed No Missing Codes
0 to 70°C
–55 to +125°C
DC Noise
+25°C
0 to 70°C
–55 to +125°C
Offset Error
+25°C
0 to 70°C
–55 to +125°C
Gain Error
+25°C
0 to 70°C
–55 to +125°C
–0.90
–0.90
–1.0
—
—
—
14
14
—
—
—
—
—
—
—
—
—
±0.5
±0.5
±0.6
±2.5
±2.5
±2.5
—
—
1.0
1.0
1.25
±0.6
±0.6
±0.6
±1.00
±1.35
±1.35
+.90
+.90
+1.0
—
—
—
—
—
1.6
2.0
2.5
±1.25
±1.25
±1.45
±2.8
±2.8
±2.8
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
%FSR
%FSR
%FSR
%FSR
%FSR
%FSR
+2.4
+4.5
—
—
—
—
—
—
—
—
+0.4
+0.1
Volts
Volts
Volts
Volts
+3.5
—
—
—
—
—
—
—
—
+.80
+10
–10
Volts
Volts
uA
uA
MIN.
0.350
—
—
TYP.
2.8
5000
10
MAX.
—
—
—
UNITS
Volts p-p
Ohm
pF
—
—
—
–76
–76
–74
—
—
—
dB
dB
dB
—
—
—
–76
–76
–74
—
—
—
dB
dB
dB
—
—
—
—
—
—
–75
–75
–74
–76
–76
–74
—
—
—
—
—
—
dB
dB
dB
dB
dB
dB
73
73
70
73
73
70
75
75
73
75
75
73
—
—
—
—
—
—
dB
dB
dB
dB
dB
dB
2.35
2.35
2.35
—
2.4
2.4
2.4
1.0
2.45
2.45
2.45
—
Volts
Volts
Volts
mA
—
—
—
—
—
—
71
71
70
71
71
70
—
—
—
—
—
—
dB
dB
dB
dB
dB
dB
2
®
®
ADCDS-1403
initial offset and gain errors can be reduced to zero using the
FINE GAIN ADJUST (pin1) and OFFSET ADJUST (pin 2)
features.
Direct Mode (AC Coupled)
—
—
—
—
+40
–27
0.50
±0.02
+46
–35
0.60
±0.03
mA
mA
Watts
%
FSR/
%
V
POWER REQUIREMENTS
Power Supply Current
+12V Supply
Power Supply Current
+5V Supply
–5V Supply
Power Dissipation
Power Supply Rejection
(5%) @ +25°C
ENVIRONMENTAL
Operating Temperature Range
ADCDS-1403
ADCDS-1403EX
Storage Temperature
Package Type
Weight
MIN.
—
TYP.
+13
MAX.
+16
UNITS
mA
This is the most common input configuration as it allows the
ADCDS-1403 to interface directly to the output of the CCD with
a minimum amount of analog "front-end" circuitry. This mode
of operation is used with full-scale video input signals from
0.350Vp-p to 2.8Vp-p.
Figure 2a. describes the typical configuration for applications
using a video input signal with a maximum amplitude of
0.350Vp-p. The coarse gain of the input amplifier is
determined from the following equation:
V
OUT
= 2.8Vp-p = V
IN
*(1+(523/75)), with all internal resistors
having a 1% tolerance. Additional fine gain adjustment can be
accomplished using the Fine Gain Adjust (pin 1 see Figure 5).
Figure 2b. describes the typical configuration for applications
using a video input signal with an amplitude greater than
0.350Vp-p and less than 2.8Vp-p. Using a single external
series resistor (see Figure 4.), the coarse gain of the ADCDS-
1403 can be set, with additional fine gain adjustments being
made using the Fine Gain Adjust function (pin 1 see Figure 5).
The coarse gain of the input amplifier can be determined from
the following equation:
V
OUT
= 2.8Vp-p = V
IN
*(1+(523/(75+Rext))), with all internal
resistors having a 1% tolerance.
4
759
5239
0
–55
–65
—
—
—
+70
+125
+150
°C
°C
°C
40-pin, TDIP
16.10 grams
TECHNICAL NOTES
1. Obtaining fully specified performance from the
ADCDS-1403 requires careful attention to pc-card layout
and power supply decoupling. The device's analog and
digital grounds are connected to each other internally.
Depending on the level of digital switching noise in the
overall CCD system, the performance of the ADCDS-1403
may be improved by connecting all ground pins
(7,32,33,35, 37) to a large
analog
ground plane beneath
the package. The use of a single +5V
analog
supply for
both the +5V
A
(pin 36) and +5V
D
(pin 34) may also be
beneficial.
2. Bypass all power supplies to ground with a 4.7μf tantalum
capacitor in parallel with a 0.1μf ceramic capacitor. Locate
the capacitors as close to the package as possible.
3. If using the suggested offset and gain adjust circuits
(Figure 3 & 5), place them as close to the ADCDS-1403's
package as possible.
4. A0 and A1 (pins 30, 31) should be bypassed with 0.1μf
capacitors to ground to reduce susceptibility to noise.
ADCDS-1403 Modes of Operation
The input amplifier stage of the ADCDS-1403 provides the
designer with a tremendous amount of flexibility. The
architecture of the ADCDS-1403 allows its input-amplifier to
be configured in any of the following configurations:
•
Direct Mode (AC coupled)
•
Non-Inverting Mode
•
Inverting Mode
When applying inputs which are less than 2.8Vp-p, a coarse
gain adjustment (applying an external resistor to pin 4) must
be performed to ensure that the full scale video input signal
(saturated signal) produces a 2.8Vp-p signal at the input-
amplifier's output (V
out
).
In all three modes of operation, the video portion of the signal
at the CDS input (i.e. input-amplifier's V
out
) must be more
negative than its associated reference level and V
out
should
not exceed ±2.8V DC.
The ADCDS-1403 achieves it specified accuracies without the
need for external calibration. If required, the device's small
V
IN
NO CONNECT
3
5
0.01µF
V
OUT
= 2.8Vp-p
5k9
Figure 2a.
Rext
4
759
5239
V
IN
NO CONNECT
3
5
0.01µF
V
OUT
= 2.8Vp-p
5k9
Figure 2b.
Rext
759
5239
4
NO CONNECT
V
IN
3
5
0.01µF
V
OUT
= 2.8Vp-p
5k9
Figure 2c.
3
®
®
ADCDS-1403
Non-Inverting Mode
The non-inverting mode of the ADCDS-1403 allows the
designer to either attenuate or add non-inverting gain to the
video input signal. This configuration also allows bypassing
the ADCDS-1403's internal coupling capacitor, allowing the
user to provide an external capacitor of appropriate value.
Figure 2c. describes the typical configuration for applications
using video input signals with amplitudes greater than
0.350Vp-p and less than 2.8Vp-p (with common mode limit of
±2.5V DC). Using a single external series resistor (see
Figure 4.), the coarse gain of the ADCDS-1403 can be set
with additional fine gain adjustments being made using the
Fine Gain Adjust function (pin 1 see Figure 5). The coarse
gain of the circuit can be determined from the following
equation:
V
OUT
= 2.8Vp-p = V
IN
*(1+(523/(75+Rext))), with all internal
resistors having a 1% tolerance.
Figure 2d. describes the typical configuration for applications
using a video input signal whose amplitude is greater than
2.8Vp-p. Using a single external series resistor (Rext 1) in
conjunction with the internal 5K (1%) resistor to ground, an
attenuation of the input signal can be achieved. Additional fine
gain adjustments being made using the Fine Gain Adjust
function (pin 1). The coarse gain of this circuit can be
determined from the following equation:
V
OUT
= 2.8Vp-p = [V
IN
*(5000/(Rext1+5000))]*
[1+(523/(75+Rext2))], with all internal resistors having
a 1% tolerance.
Rext2
Inverting Mode
The inverting mode of operation can be used in applications
where the analog input to the ADCDS-1403 has a video input
signal whose amplitude is more positive than its associated
reference level.
The ADCDS-1403's correlated double
sampler (i.e. input amplifier's V
OUT
) requires that the video
signal's amplitude be more negative than its reference
level at all times (see timing diagram for details).
Using the
ADCDS-1403 in the inverting mode allows the designer to
perform an additional signal inversion to correct for any
analog "front end" pre-processing that may have occurred
prior to the ADCDS-1403.
Figure 2e. describes the typical configuration for applications
using a video input signal with a maximum amplitude of
0.350Vp-p. Additional fine gain adjustments can be made
using the Fine Gain Adjust function (pin 1). The coarse gain
of this circuit can be determined from the following equation:
V
OUT
= 2.8Vp-p = –V
IN
*(523/75), with all internal resistors
having a 1% tolerance.
Figure 2f. describes the typical configuration used in
applications needing to invert video input signals whose
amplitude is greater than 0.350Vp-p. Using a single external
series resistor (see Figure 4.), the initial gain of the ADCDS-
1403 can be set, with additional fine gain adjustments being
made using the Fine Gain Adjust function (pin 1). The coarse
gain of this circuit can be determined from the following
equation:
V
OUT
= 2.8Vp-p = –V
IN
*(523/75+Rext), with all internal
resistors having a 1% tolerance.
ADCDS-1403
4
759
5239
3
NO CONNECT
Rext1
V
IN
5
0.01µF
V
OUT
= 2.8Vp-p
+5V
5k9
External
Series
Resistor
20K9
Offset
Adjust
2
Figure 2d.
759
5239
–5V
–V
IN
4
3
NO CONNECT
5
0.01µf
V
OUT
= 2.8Vp-p
Figure 3. Offset Adjustment Circuit
5k9
C o a r s e G a in A d ju s tm e n t P lo t
E x te r n a l G a in R e s is to r v s . F u ll S c a le V id e o In p u t
E x te r n a l G a in R e s is to r (O h m s )
1 0 0 0 0
D ir e c t M o d e
& N o n - In v e r tin g
M o d e
Figure 2e.
Rext
–V
IN
4
759
5239
1 0 0 0
In v e r tin g M o d e
3
NO CONNECT
5
0.01µf
V
OUT
= 2.8Vp-p
1 0 0
5k9
1 0
0 .2 5
0 .5
0 .7 5
1
1 .2 5
1 .5
1 .7 5
2
2 .2 5
2 .5
2 .7 5
3
F u ll S c a le V id e o S ig n a l (V o lts )
Figure 2f.
Figure 4. Coarse Gain Adjustment Plot
4
®
®
ADCDS-1403
Offset Adjustment
Manual offset adjustment for the ADCDS-1403 can be
accomplished using the adjustment circuit shown in Figure
3. A software controlled D/A converter can be substituted for
the 20KΩ potentiometer. The offset adjustment feature
allows the user to adjust the Offset/Dark Current level of the
ADCDS-1403 until the output bits are 00 0000 0000 0000
and the LSB flickers between 0 and 1. Offset adjust should
be performed before gain adjust to avoid interaction. The
ADCDS-1403's offset adjustment is dependent on the value
of the external series resistor used in the offset adjust circuit
(Figure 3). The Offset Adjustment graph (Figure 6) illustrates
the typical relationship between the external series resistor
value and its offset adjustment capability utilizing ±5V
supplies.
Offset Adjustment Sensitivity
It should be noted that with increasing amounts of offset
adjustment (smaller values of external series resistors), the
ADCDS-1403 becomes more susceptible to power supply
noise or voltage variations seen at the wiper of the offset
potentiometer.
ADCDS-1403
+5V
20K9
Fine
Gain
Adjust
1
For Example:
External 50KΩ resistor:
Ω
1. 10mV of noise or voltage variation at the potentiometer
will produce 0.25LSB's of output variation.
2. 100mV of noise or voltage variation at the potentiometer
will produce 2.5LSB's of output variation.
The Offset Adjustment Sensitivity graph (Figure 7) illustrates
the offset adjustment sensitivity over a wide range of external
resistor and noise values. If a large offset voltage is required,
it is recommended that a very low noise external reference
be used in the offset adjust circuit in place of power supplies.
The ADCDS-1403's +2.4V reference output could be
configured to provide the reference voltage for this type of
application.
Fine Gain Adjustment
Fine gain adjustment (pin 1) is provided to compensate for
the tolerance of the external coarse gain resistor (Rext) and/
or the unavailability of exact coarse gain resistor (Rext)
values. Note, the fine gain adjustment will not change the
expected input amplifier's full scale V
OUT
(2.8Vp-p.) Instead,
the gain of the ADCDS-1403's internal A/D is adjusted
allowing the actual input amplifier's full scale V
OUT
to
produce an output code of all ones (11 1111 1111 1111).
Fine gain adjustment for the ADCDS-1403 is accomplished
using the adjustment circuit shown below (Figure 5). A
software controlled D/A converter can be substituted for the
20KΩ potentiometer. The fine gain adjust circuit ensures that
the video input signal (saturated signal) will be properly
scaled to obtain the desired Full Scale digital output of 11
1111 1111 1111, with the LSB flickering between 0 and 1. Fine
gain adjust should be performed following the offset adjust
–5V
Figure 5. Fine Gain Adjustment Circuit
Offset Adjustment vs. External Series Resistor
10000
±LSB's of Adjustment
Output Variation (LSB's)
Offset Adjustment Sensitivity
External Series Resistor vs. Output Variation (LSB's)
100
Peak-Peak
variation at
potentiometer
100mV
1000
10
1
100
0.1
10mV
10
0.01
1mV
0
5K
10K 15K 20K 25K 30K 35K 40K 45K 50K 55K 60K
0
5k
10k 15k
20k 25k
30k 35k
40k 45k
50k
55k 60k
External Series Resistor (Ohm's)
External Series Resistor Value (Ohms)
Figure 6. Offset Adjustment vs. External Series Resistor
Figure 7. Offset Adjustment Sensitivity
5
stm32/stm8
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