INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT73
Dual JK flip-flop with reset;
negative-edge trigger
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors
Product specification
Dual JK flip-flop with reset; negative-edge trigger
FEATURES
•
Output capability: standard
•
I
CC
category: flip-flops
GENERAL DESCRIPTION
The 74HC/HCT73 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
74HC/HCT73
The 74HC/HCT73 are dual negative-edge triggered
JK-type flip-flops featuring individual J, K, clock (nCP) and
reset (nR) inputs; also complementary Q and Q outputs.
The J and K inputs must be stable one set-up time prior to
the HIGH-to-LOW clock transition for predictable
operation.
The reset (nR) is an asynchronous active LOW input.
When LOW, it overrides the clock and data inputs, forcing
the Q output LOW and the Q output HIGH.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
TYPICAL
SYMBOL
t
PHL
/ t
PLH
PARAMETER
propagation delay
nCP to nQ
nCP to nQ
nR to nQ, nQ
f
max
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
maximum clock frequency
input capacitance
power dissipation capacitance per flip-flop
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
16
16
15
77
3.5
30
15
18
15
79
3.5
30
ns
ns
ns
MHz
pF
pF
HCT
UNIT
December 1990
2
Philips Semiconductors
Product specification
Dual JK flip-flop with reset; negative-edge trigger
PIN DESCRIPTION
PIN NO.
1, 5
2, 6
4
11
12, 9
13, 8
14, 7, 3, 10
SYMBOL
1CP, 2CP
1R, 2R
V
CC
GND
1Q, 2Q
1Q, 2Q
1J, 2J, 1K, 2K
NAME AND FUNCTION
74HC/HCT73
clock input (HIGH-to-LOW, edge-triggered)
asynchronous reset inputs (active LOW)
positive supply voltage
ground (0 V)
true flip-flop outputs
complement flip-flop outputs
synchronous inputs; flip-flops 1 and 2
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
Dual JK flip-flop with reset; negative-edge trigger
FUNCTION TABLE
OPERATING
MODE
asynchronous reset
toggle
load “0” (reset)
load “1” (set)
hold “no change”
Notes
INPUTS
nR
L
H
H
H
H
nCP
X
↓
↓
↓
↓
J
X
h
l
h
l
K
X
h
h
l
l
74HC/HCT73
OUTPUTS
Q
L
q
L
H
q
Q
H
q
H
L
q
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP
transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the HIGH-to-LOW CP
transition
q = lower case letters indicate the state of the referenced output one
set-up time prior to the HIGH-to-LOW CP transition
X = don’t care
↓
= HIGH-to-LOW CP transition
Fig.4 Functional diagram.
Fig.5 Logic diagram (one flip-flop).
December 1990
4
Philips Semiconductors
Product specification
Dual JK flip-flop with reset; negative-edge trigger
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
I
CC
category: flip-flops
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
T
amb
(°C)
74HC
SYMBOL PARAMETER
min.
t
PHL
/ t
PLH
propagation delay
nCP to nQ
propagation delay
nCP to nQ
propagation delay
nR to nQ, nQ
output transition time
+25
typ.
52
19
15
52
19
15
50
18
14
19
7
6
80
16
14
80
16
14
80
16
14
80
16
14
3
3
3
6.0
30
35
22
8
6
22
8
6
22
8
6
22
8
6
−8
−3
−2
23
70
83
−40
to
+85
max. min.
160
32
27
160
32
27
145
29
25
75
15
13
100
20
17
100
20
17
100
20
17
100
20
17
3
3
3
4.8
24
28
max.
200
40
34
200
40
34
180
36
31
95
19
16
120
24
20
120
24
20
120
24
20
120
24
20
3
3
3
4.0
20
24
−40
to
+125
min. max.
240
48
41
240
48
41
220
44
38
110
22
19
ns
UNIT
74HC/HCT73
TEST CONDITIONS
V
CC
(V)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
WAVEFORMS
Fig.6
t
PHL
/ t
PLH
ns
Fig.6
t
PHL
/ t
PLH
ns
Fig.7
t
THL
/ t
TLH
ns
Fig.6
t
W
clock pulse width
HIGH or LOW
reset pulse width
HIGH or LOW
removal time
nR to nCP
set-up time
nJ, nK to nCP
hold time
nJ, nK to nCP
maximum clock pulse
frequency
ns
Fig.6
t
W
ns
Fig.7
t
rem
ns
Fig.7
t
su
ns
Fig.6
t
h
ns
Fig.6
f
max
MHz
Fig.6
December 1990
5
京公网安备 11010802033920号
EEWORLD
