54122-418-20-1250R datasheet, PDF

54122-418-20-1250R: DescriptionBoard Stacking Connector, 20 Contact(s), 2 Row(s), Male, Straight, 0.1 inch Pitch, Solder Terminal, Locking, Black Insulator, Receptacle,; CategoryThe connector The connector; File Size66KB，1 Pages; ManufacturerAmphenol; Websitehttp://www.amphenol.com/

Download Datasheet Parametric View All

54122-418-20-1250R Overview

Board Stacking Connector, 20 Contact(s), 2 Row(s), Male, Straight, 0.1 inch Pitch, Solder Terminal, Locking, Black Insulator, Receptacle,

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Objectid	1621046328
Reach Compliance Code	compliant
Country Of Origin	France
ECCN code	EAR99
YTEOL	8.65
Other features	UNSHROUDED
body width	0.19 inch
subject depth	0.492 inch
body length	2 inch
Body/casing type	RECEPTACLE
Connector type	BOARD STACKING CONNECTOR
Contact to complete cooperation	TIN LEAD OVER NICKEL (50)
Contact completed and terminated	Tin/Lead (Sn/Pb) - with Nickel (Ni) barrier
Contact point gender	MALE
Contact material	PHOSPHOR BRONZE
contact mode	RECTANGULAR
Contact style	SQ PIN-SKT
DIN compliance	NO
Filter function	NO
IEC compliance	NO
Insulation resistance	5000000000 Ω
Insulator color	BLACK
insulator material	POLYETHYLENE
JESD-609 code	e0
MIL compliance	NO
Manufacturer's serial number	54122
Plug contact pitch	0.1 inch
Match contact row spacing	0.1 inch
Mixed contacts	NO
Installation option 1	LOCKING
Installation method	STRAIGHT
Installation type	BOARD
Number of connectors	ONE
PCB row number	2
Number of rows loaded	2
Maximum operating temperature	125 °C
Minimum operating temperature	-65 °C
Options	GENERAL PURPOSE
PCB contact pattern	RECTANGULAR
PCB contact row spacing	2.54 mm
Plating thickness	79u inch
Rated current (signal)	3 A
Guideline	UL, CSA
reliability	COMMERCIAL
Terminal length	0.12 inch
Terminal pitch	2.54 mm
Termination type	SOLDER
Total number of contacts	20
UL Flammability Code	94V-0

PDM: Rev:G

STATUS:

Released

Printed: Jun 23, 2006

[Repost] Understanding crystal growth and wafer preparation in one article: How are wafers grown? How are they prepared? This article covers the process of converting sand into semiconductor-grade silicon, which is then converted into crystals and wafers, and the process step...; 皇华Ameya360 Analog electronics

Does Cosmic have instructions for defining bit operations similar to Keil's sbit?: Does Cosmic have instructions for defining bit operations similar to Keil's sbit?...; joalin stm32/stm8

[I contribute to the Xilinx Resource Center] Technical documentation for the Spartan 3E board: Technical documentation for the Spartan 3E board...; wanghongyang FPGA/CPLD

About the logo problem of transplanting uclinux startup part: The version is linux-2.4.x. I modified some codes according to the reference materials. After make, the printed information does not have the common ucliux logo. I directly enter the Sash command shel...; zl0801 Linux and Android

The power plane is clearly more than adequate, so why is the DC voltage drop so critical?: Original article by Mr. Gaosu | Jiang JieNew year, new atmosphere, new problems in board modification. You may not believe it, but at 90A current, the power plane has two layers of 2oz copper, and the...; yvonneGan PCB Design

Help others and achieve self-realization——EEWORLD Q&A List (9th issue): [size=4][backcolor=red][/backcolor][/size] [size=4][backcolor=red][color=#ffffff][b] ＊[/b][b]＊[/b][b]＊[/b][b]Activity Rules[/b][b]＊[/b][b]＊[/b][b]＊[/b][/color][/backcolor] The new activity rules will ...; okhxyyo Talking

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components