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5962F9652101QXC

Description
NAND Gate, ACT Series, 3-Func, 3-Input, CMOS, CDFP14, BOTTOM BRAZED, CERAMIC, DFP-14
Categorylogic    logic   
File Size225KB,9 Pages
ManufacturerCobham Semiconductor Solutions
Download Datasheet Parametric View All

5962F9652101QXC Overview

NAND Gate, ACT Series, 3-Func, 3-Input, CMOS, CDFP14, BOTTOM BRAZED, CERAMIC, DFP-14

5962F9652101QXC Parametric

Parameter NameAttribute value
MakerCobham Semiconductor Solutions
Parts packaging codeDFP
package instructionDFP,
Contacts14
Reach Compliance Codeunknown
seriesACT
JESD-30 codeR-CDFP-F14
JESD-609 codee4
Logic integrated circuit typeNAND GATE
Number of functions3
Number of entries3
Number of terminals14
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDFP
Package shapeRECTANGULAR
Package formFLATPACK
propagation delay (tpd)16 ns
Certification statusNot Qualified
Maximum seat height2.921 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal surfaceGOLD
Terminal formFLAT
Terminal pitch1.27 mm
Terminal locationDUAL
total dose300k Rad(Si) V
width6.2865 mm
Base Number Matches1
Standard Products
UT54ACS10/UT54ACTS10
Triple 3-Input NAND Gates
Datasheet
November 2010
www.aeroflex.com/logic
FEATURES
1.2μ
CMOS
- Latchup immune
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 14-pin DIP
- 14-lead flatpack
UT54ACS10 - SMD 5962-96520
UT54ACTS10 - SMD 5962-96521
DESCRIPTION
The UT54ACS10 and the UT54ACTS10 are triple three-input
NAND gates. The circuits perform the Boolean functions
Y = A⋅B⋅C or Y = A + B + C in positive logic.
The devices are characterized over full military temperature
range of -55°C to +125°C.
FUNCTION TABLE
INPUTS
A
H
L
X
X
B
H
X
L
X
C
H
X
X
L
OUTPUT
Y
L
H
H
H
PINOUTS
14-Pin DIP
Top View
A1
B1
A2
B2
C2
Y2
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
DD
C1
Y1
C3
B3
A3
Y3
14-Lead Flatpack
Top View
A1
B1
A2
B2
C2
Y2
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
DD
C1
Y1
C3
B3
A3
Y3
LOGIC DIAGRAM
A1
B1
C1
Y1
LOGIC SYMBOL
A1
B1
C1
A2
B2
C2
A3
B3
C3
(1)
(2)
(13)
(3)
(4)
(5)
(9)
(10)
(11)
(8)
Y3
(6)
Y2
&
(12)
Y1
A2
B2
C2
A3
B3
C3
Y2
Y3
Note:.
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and
IEC Publication 617-12.
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