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GS71108AGP-6IT

Description
Standard SRAM, 128KX8, 6ns, CMOS, PDSO32, 0.400 INCH, TSOP2-32
Categorystorage    storage   
File Size466KB,15 Pages
ManufacturerGSI Technology
Websitehttp://www.gsitechnology.com/
Environmental Compliance  
Download Datasheet Parametric View All

GS71108AGP-6IT Overview

Standard SRAM, 128KX8, 6ns, CMOS, PDSO32, 0.400 INCH, TSOP2-32

GS71108AGP-6IT Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerGSI Technology
Parts packaging codeTSOP2
package instructionTSOP2,
Contacts32
Reach Compliance Codecompliant
ECCN code3A991.B.2.B
Maximum access time6 ns
JESD-30 codeR-PDSO-G32
JESD-609 codee3
length20.95 mm
memory density1048576 bit
Memory IC TypeSTANDARD SRAM
memory width8
Humidity sensitivity level3
Number of functions1
Number of terminals32
word count131072 words
character code128000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize128KX8
Package body materialPLASTIC/EPOXY
encapsulated codeTSOP2
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)260
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfacePURE MATTE TIN
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width10.16 mm
Base Number Matches1
GS71108ATP/J/SJ/U
SOJ, TSOP, FP-BGA
Commercial Temp
Industrial Temp
Features
• Fast access time: 6, 8, 10, 12 ns
• CMOS low power operation: 160/120/95/80 mA at minimum
cycle time
• Single 3.3 V power supply
• All inputs and outputs are TTL-compatible
• Fully static operation
• Industrial Temperature Option:
–40°
to 85°C
• Package line up
J: 400 mil, 32-pin SOJ package
TP: 400 mil, 32-pin TSOP Type II package
SJ: 300 mil, 32-pin SOJ package
U: 6 mm x 8 mm Fine Pitch Ball Grid Array package
128K x 8
1Mb Asynchronous SRAM
A
3
A
2
A
1
A
0
CE
DQ
1
DQ
2
V
DD
V
SS
DQ
3
DQ
4
WE
A
16
A
15
A
14
A
13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
6, 8, 10, 12 ns
3.3 V V
DD
Center V
DD
and V
SS
32
31
30
29
A
4
A5
A6
A
7
OE
DQ
8
DQ
7
V
SS
V
DD
DQ6
DQ
5
A
8
A
9
A
10
A
11
A
12
SOJ & TSOP-II 128K x 8-Pin Configuration
32-pin
400 mil SOJ
&
300 mil SOJ
&
400 mil TSOP II
28
27
26
25
24
23
22
21
20
19
18
17
Description
The GS71108A is a high speed CMOS Static RAM organized
as 131,072 words by 8 bits. Static design eliminates the need
for external clocks or timing strobes. The GS operates on a
single 3.3 V power supply and all inputs and outputs are TTL-
compatible. The GS71108A is available in a 6 mm x 8 mm
Fine Pitch BGA package, as well as in 300 mil and 400 mil
SOJ and 400 mil TSOP Type-II packages.
Packages J, TP, and SJ
Fine Pitch BGA 128K x 8-Bump Configuration
1
A
NC
DQ
1
DQ
2
V
SS
V
DD
DQ
3
DQ
4
NC
2
OE
NC
NC
NC
NC
NC
NC
A
10
3
A
2
A
1
A
0
NC
NC
A
14
A
15
A
16
4
A
6
A
5
A
4
A
3
NC
A
11
A
12
A
13
5
A
7
CE
NC
NC
NC
DQ
5
WE
A
9
6
NC
DQ
8
DQ
7
V
DD
V
SS
DQ
6
A
8
NC
Pin Descriptions
Symbol
A
0
–A
16
DQ
1
–DQ
8
CE
WE
OE
V
DD
V
SS
NC
Description
Address input
Data input/output
Chip enable input
Write enable input
Output enable input
+3.3 V power supply
Ground
No connect
B
C
D
E
F
G
H
Package U
6 mm x 8 mm, 0.75 mm Bump Pitch
Top View
Rev: 1.03 3/2002
1/15
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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