HIGH-SPEED 4K X 16
SEQUENTIAL ACCESS
RANDOM ACCESS MEMORY (SARAM
™
)
Integrated Device Technology, Inc.
IDT70824S/L
FEATURES:
• 4K x 16 Sequential Access Random Access Memory
(SARAM
™
)
- Sequential Access from one port and standard Random
Access from the other port
- Separate upper-byte and lower-byte control of the
Random Access Port
• High speed operation
- 20ns t
AA
for random access port
- 20ns t
CD
for sequential port
- 25ns clock cycle time
• Architecture based on Dual-Port RAM cells
• Electrostatic discharge > 2001V, Class II
• Compatible with Intel BMIC and 82430 PCI Set
• Width and Depth Expandable
• Sequential side
- Address based flags for buffer control
- Pointer logic supports up to two internal buffers
• Battery backup operation - 2V data retention
• TTL-compatible, single 5V (+10%) power supply
• Available in 80-pin TQFP and 84-pin PGA
• Military product compliant to MIL-STD-883.
• Industrial temperature range (–40°C to +85°C) is available,
tested to military electrical specifications.
DESCRIPTION:
The IDT70824 is a high-speed 4K x 16-bit Sequential
Access Random Access Memory (SARAM). The SARAM
offers a single-chip solution to buffer data sequentially on one
port, and be accessed randomly (asynchronously) through
the other port. The device has a Dual-Port RAM based
architecture with a standard SRAM interface for the random
(asynchronous) access port, and a clocked interface with
counter sequencing for the sequential (synchronous) access
port.
Fabricated using CMOS high-performance technology,
this memory device typically operates on less than 900mW of
power at maximum high-speed clock-to-data and Random
Access. An automatic power down feature, controlled by
CE
,
permits the on-chip circuitry of each port to enter a very low
standby power mode.
The IDT70824 is packaged in a 80-pin Thin Plastic Quad
Flatpack (TQFP) or 84-pin Ceramic Pin Grid Array (PGA).
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B, making it ideally
suited to military temperature applications demanding the
highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
A
0-11
12
RST
SCLK
Random
Access
Port
Controls
Sequential
Access
Port
Controls
CE
OE
R/
W
LB
LSB
UB
MSB
CMD
I/O0-15
4K X 16
Memory
Array
16
12
CNTEN
SOE
SSTRT
1
SSTRT
2
SCE
SR/
W
SLD
SI/O0-15
Data
L
Addr
L
12
Data
R
Addr
R
16
Reg.
12
16
RST
12
12
12
Pointer/
Counter
Start Address for Buffer #1
End Address for Buffer #1
Start Address for Buffer #2
End Address for Buffer #2
Flow Control Buffer
Flag Status
12
EOB
1
COMPARATOR
EOB
2
3099 drw 01
The IDT logo is a registered trademark and SARAM is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
OCTOBER 1996
DSC-3099/3
6.30
1
IDT70824S/L
HIGH-SPEED 4K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
(1,2)
INDEX
SI/O
1
SI/O
0
GND
N/C
SI/O
2
SI/O
3
V
CC
SI/O
4
SI/O
5
SI/O
6
SI/O
7
GND
SI/O
8
SI/O
9
SI/O
10
SI/O
11
V
CC
SI/O
12
SI/O
13
SI/O
14
SI/O
15
GND
N/C
GND
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
60
59
2
58
3
1
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
57
56
55
54
53
SCE
RST
SR/
W
SSTRT
2
SSTRT
1
SLD
IDT70824
PN80-1
TQFP
TOP VIEW(3)
52
51
50
49
48
47
46
45
44
43
42
CNTEN
GND
GND
SOE
SCLK
GND
EOB
2
EOB
1
V
CC
I/O
0
CMD
CE
LB
UB
R/
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
V
CC
V
CC
A
1
A
0
41
20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
OE
W
I/O
1
GND
I/O
2
I/O
3
V
CC
I/O
4
I/O
5
I/O
6
I/O
7
GND
I/O
8
I/O
9
I/O
10
I/O
11
V
CC
I/O
12
I/O
13
I/O
14
I/O
15
GND
63
61
60
58
55
54
48
46
3099 drw 02
I/O
1
66
V
CC
64
EOB
1
62
51
45
42
GND
CNTEN
GND
SSTRT
2
SR/W NC
59
56
GND
43
NC
40
11
10
09
08
07
06
05
04
03
02
01
I/O
2
67
NC
65
I/O
0
EOB
2
SOE
49
RST
SLD SCE
52
50
47
44
SI/O
0
SI/O
1
SI/O
3
41
39
57
53
I/O
3
GND
69
68
SCLK GND
SSTRT
1
SI/O
2
V
CC
38
37
I/O
4
72
V
CC
71
73
33
SI/O
4
SI/O
5
35
34
I/O
7
75
I/O
6
GND
70
74
IDT70824
G84-3
84-PIN PGA
TOP VIEW
(3)
SI/O
8
SI/O
7
GND
32
31
36
I/O
9
76
I/O
5
77
I/O
8
78
SI/O
9
SI/O
10
SI/O
6
28
29
30
I/O
10
I/O
11
V
CC
79
80
SI/O
12
V
CC
SI/O
11
26
27
I/O
12
I/O
13
81
83
7
SI/O
14
SI/O
13
I/O
14
82
1
NC
2
CMD
A
0
11
12
23
25
V
CC
10
A
2
14
17
20
NC SI/O
15
22
24
I/O
15
GND
84
3
OE
5
LB
8
V
CC
15
A
4
13
A
7
16
A
10
18
GND GND
19
21
NC
A
INDEX
R/
W
4
UB
C
6
CE
D
9
A
1
E
A
5
F
A
3
G
A
6
H
A
8
J
A
9
K
A
11
L
B
3099 drw 03
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. This text does not indicate orientation of the actual part-marking.
6.30
2
IDT70824S/L
HIGH-SPEED 4K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTIONS: RANDOM ACCESS PORT
SYMBOL
A
0
-A
11
CE
NAME
Address Lines
Chip Enable
I/O
(1)
I
I
I
DESCRIPTION
Address inputs to access the 4096-word (16 bit) memory array.
Random access data inputs/outputs for 16-bit wide data.
When
CE
is LOW, the random access port is enabled. When
CE
is HIGH, the random access
port is disabled into power-down mode and the I/O outputs are in the high-impedance state. All
data is retained during
CE
= VIH, unless it is altered by the sequential port.
CE
and
CMD
may not
be LOW at the same time.
When
CMD
is LOW, Address lines A
0
-A
2
, R/
W
, and inputs/outputs I/
O0
-I/
O11
, are used to
access the control register, the flag register, and the start and end of buffer registers.
CMD
and
CE
may not be LOW at the same time.
If
CE
is LOW and
CMD
is HIGH, data is written into the array when R/
W
is LOW and read out of the
array when R/
W
is HIGH. If
CE
is HIGH and
CMD
is LOW, R/
W
is used to access the buffer com-
mand registers.
CE
and
CMD
may not be LOW at the same time.
When
OE
is LOW and R/
W
is HIGH, I/O0-I/O15 outputs are enabled. When
OE
is HIGH, the I/O
outputs are in the high-impedance state.
When
LB
is LOW, I/O0-I/O7 are accessible for read and write operations. When
LB
is HIGH, I/
O0
-
I/
O7
are tri-stated and blocked during read and write operations.
UB
controls access for I/O8-
I/
O15
in the same manner and is asynchronous from
LB
.
Seven +5V power supply pins. All Vcc pins must be connected to the same +5V V
CC
supply.
Ten Ground pins. All Ground pins must be connected to the same Ground supply.
3099 tbl 01
I/
O0
-I/
O15
Inputs/Outputs
CMD
Control Register
Enable
Read/Write Enable
I
R/
W
I
OE
Output Enable
Lower Byte, Upper
Byte Enables
Power Supply
Ground
I
I
LB UB
,
V
CC
GND
PIN DESCRIPTIONS: SEQUENTIAL ACCESS PORT
SYMBOL
NAME
SI/O0-15 Inputs
SCLK
Clock
I/O
(1)
DESCRIPTION
I/O Sequential data inputs/outputs for 16-bit wide data.
I
SI/
O0
-SI/
O15
,
SCE
, SR/
W
, and
SLD
are registered on the LOW-to-HIGH transition of SCLK.
Also, the sequential access port address pointer increments by 1 on each LOW-to-HIGH
transition of SCLK when
CNTEN
is LOW.
Chip Enable
I
When
SCE
is LOW, the sequential access port is enabled on the LOW-to-HIGH transition of
SCLK. When
SCE
is HIGH, the sequential access port is disabled into powered-down mode on
the LOW-to-HIGH transition of SCLK, and the SI/O outputs are in the high-impedance state. All
data is retained, unless altered by the random access port.
Counter Enable
I
When
CNTEN
is LOW, the address pointer increments on the LOW-to-HIGH transition of SCLK.
This function is independant of
SCE
.
Read/Write Enable
I
When SR/
W
and SCE are LOW, a write cycle is initiated on the LOW-to-HIGH transition of
SCLK. When SR/
W
is HIGH, and
SCE
and
SOE
are LOW, a read cycle is initiated on the
LOW-to-HIGH transition of SCLK. Termination of a Write cycle is done on the Low-to-High
transistion of SCLK if SR/
W
or
SCE
is High.
Address Pointer
I
When
SLD
is sampled LOW, there is an internal delay of one cycle before the address pointer
Load Control
changes. When
SLD
is LOW, data on the inputs SI/
O0
-SI/
O11
is loaded into a data-in register
on the LOW-to-HIGH transition of SCLK. On the cycle following
SLD
, the address pointer
changes to the address location contained in the data-in register.
SSTRT
1
and
SSTRT
2
may
not be LOW while
SLD
is LOW or during the cycle following
SLD
.
Load Start of
I
When
SSTRT
1
or
SSTRT
2
is LOW, the start of address register #1 or #2 is loaded into the
Address Register
address pointer on the LOW-to-HIGH transition of SCLK. The start addresses are stored in
internal registers.
SSTRT
1
and
SSTRT
2
may not be LOW while
SLD
is LOW or during the cycle
following
SLD
.
End of Buffer Flag
O
EOB
1
or
EOB
2
is output LOW when the address pointer is incremented to match the address
stored in the end of buffer registers. The flags can be cleared by either asserting
RST
LOW or
by writing zero into bit 0 and/or bit 1 of the control register at address 101.
EOB
1
and
EOB
2
are
dependent on separate internal registers, and therefore separate match addresses.
Output Enable
I
SOE
controls the data outputs and is independent of SCLK. When
SOE
is LOW, output buffers
and the sequentially addressed data is output. When
SOE
is HIGH, the SI/O output bus is in
the high-impedance state.
SOE
is asynchronous to SCLK.
Reset
I
When
RST
is LOW, all internal registers are set to their default state, the address pointer is set
to zero and the
EOB
1
and
EOB
2
flags are set HIGH.
RST
is asynchronous to SCLK.
3099 tbl 02
SCE
CNTEN
SR/
W
SLD
1,
SSTRT
2
SSTRT
1,
EOB
2
EOB
SOE
RST
NOTE
:
1. "I/O" is bidirectional Input and Output. "I" is Input and "O" is Output.
6.30
3
IDT70824S/L
HIGH-SPEED 4K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
(2)
Rating
Commercial
Military
–0.5 to +7.0
Unit
V
Terminal Voltage –0.5 to +7.0
with Respect
to GND
Operating
Temperature
Temperature
Under Bias
Storage
Temperature
DC Output
Current
0 to +70
–55 to +125
–55 to +125
50
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Military
Commercial
Ambient
Temperature
–55°C to +125°C
0°C to +70°C
GND
0V
0V
VCC
5.0V
±
10%
5.0V
±
10%
3099 tbl 04
T
A
T
BIAS
T
STG
I
OUT
–55 to +125
–65 to +135
–65 to +150
50
°C
°C
°C
mA
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
–0.5
(1)
Typ.
5.0
0
—
—
Max.
5.5
0
6.0
(2)
0.8
Unit
V
V
V
V
3099 tbl 05
NOTES:
3099 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. V
TERM
must not exceed Vcc + 0.5V for more than 25% of the cycle time
or 10ns maximum, and is limited to < 20mA for the period of V
TERM
> Vcc
+ 0.5V.
NOTES:
1. V
IL
> –1.5V for pulse width less than 10ns.
2. V
TERM
must not exceed Vcc + 0.5V.
CAPACITANCE
(1)
(T
A
= +25°C, F = 1.0MHz)TQFP ONLY
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output
Capacitance
Conditions
(2)
V
IN
= 3dV
V
OUT
= 3dV
Max.
9
10
Unit
pF
pF
NOTES:
3099 tbl 06
1. This parameter is determined by device characterization, but is not
production tested.
2. 3dV references the interpolated capacitance when the input and output
signals switch from 0V to 3V or from 3V to 0V.
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (V
CC
= 5.0V
±
10%)
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
(1)
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Conditions
V
CC
= Max. V
IN
= GND to V
CC
V
CC
= Max.
CE
and
SCE
= V
IH
V
OUT
= GND to V
CC
I
OL
= 4mA, V
CC
= Min.
I
OH
= –4mA, V
CC
= Min.
IDT70824S
Min.
Max.
—
—
—
2.4
5.0
5.0
0.4
—
IDT70824L
Min.
Max.
—
—
—
2.4
1.0
1.0
0.4
—
Unit
µA
µA
V
V
3099 tbl 07
NOTE:
1. At Vcc
≤
2.0V input leakages are undefined.
6.30
4
IDT70824S/L
HIGH-SPEED 4K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE
AND SUPPLY VOLTAGE RANGE
(1)
(VCC = 5.0V
±
10%)
Symbol
I
CC
Parameter
Dynamic Operating
Current
(Both Ports Active)
I
SB
1
Standby Current
(Both Ports - TTL Level
Inputs)
I
SB
2
Standby Current
(One Port - TTL Level
Input)
I
SB
3
Full Standby Current
(Both Ports - CMOS
Level Inputs)
I
SB
4
Full Standby Current
(One Port - CMOS
Level Inputs)
CE
Test
Condition
= V
IL
, Outputs
Open,
SCE
= V
IL
(5)
f = f
MAX
(3)
SCE
Version
MIL.
S
L
70824X20
70824X25
Com'l. Only Com'l. Only
Typ.
(2)
Max. Typ.
(2)
Max.
—
—
180
180
—
—
25
25
—
115
115
—
—
1.0
0.2
—
—
110
110
—
—
380
330
—
—
70
50
—
——
260
230
—
—
15
5
—
—
240
200
—
—
170
170
—
—
25
25
—
—
105
105
—
—
1.0
0.2
—
—
100
100
—
—
360
310
—
—
70
50
—
—
250
220
—
—
15
5
—
—
230
190
70824X35
70824X45
Typ.
(2)
Max. Typ.
(2)
Max. Unit
160
160
160
160
20
20
20
20
95
95
95
95
1.0
0.2
1.0
0.2
90
90
90
90
400
340
340
290
85
65
70
50
290
250
240
210
30
10
15
5
260
215
220
180
155
155
155
155
16
16
16
16
90
90
90
90
1.0
0.2
1.0
0.2
85
85
85
85
400 mA
340
340
290
85
65
70
50
290
250
240
210
30
10
15
5
260
215
220
180
mA
mA
mA
mA
and
CE
>
V
IH
(7)
MIL.
CMD
= V
IH
COM’L. S
L
S
L
f = f
MAX
(3)
CE
or
SCE
=
V
IH
Active Port Outputs
Open, f = f
MAX
(3)
COM’L. S
L
MIL.
S
L
COM’L. S
L
MIL.
S
L
Both Ports
CE
and
(6)
SCE
≥
V
CC
- 0.2V
V
IN
≥
V
CC
- 0.2V or
V
IN
≤
0.2V, f = 0
(4)
COM’L. S
L
S
L
One Port
CE
or
MIL.
(6,7)
SCE
≥
V
CC
- 0.2V
Outputs Open
(Active port), f = f
MAX
(3)
COM’L. S
V
IN
≥
V
CC
- 0.2V or
V
IN
≤
0.2V
L
NOTES:
1. 'X' in part number indicates power rating (S or L).
2. V
CC
= 5V, Ta = +25°C; guaranteed by device characterization but not production tested.
3. At f = fMAX, address, control lines (except Output Enable), and SCLK are cycling at the maximum frequency read cycle of 1/tRC.
4. f = 0 means no address or control lines change.
5.
SCE
may transition, but is Low (
SCE
=V
IL
) when clocked in by SCLK.
6.
SCE
may be
≤
0.2V, after it is clocked in, since SCLK=V
IH
must be clocked in prior to powerdown.
7. If one port is enabled (either
CE
or
SCE
= Low) then the other port is disabled (
SCE
or
CE
= High, respectively). CMOS High > Vcc - 0.2V and
Low < 0.2V, and TTL High = V
IH
and Low = V
IL
.
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(L VERSION ONLY)
(V
LC
< 0.2V, V
HC
> V
CC
- 0.2V)
Symbol
V
DR
I
CCDR
t
CDR
(3)
t
R
(3)
Parameter
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time
CE
Test Condition
V
CC
= 2V
= V
HC
MIL.
COM’L.
V
IN
= V
HC
or = V
LC
SCE
CMD
Min.
2.0
—
—
0
t
RC
(2)
Typ.
(1)
—
100
100
—
—
Max.
—
4000
1500
—
—
Unit
V
µA
ns
ns
3099 tbl 09
= V
HC
(4)
when SCLK=
> V
HC
NOTES :
1. T
A
= +25°C, V
CC
= 2V; guaranteed by device characterization but not production tested.
2. t
RC
= Read Cycle Time
3. This parameter is guaranteed by device characterization, but is not production tested.
4. To initiate data retention,
SCE
= V
IH
must be clocked in.
6.30
5
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