51745-10010819C0LF datasheet, PDF

51745-10010819C0LF: DescriptionBoard Connector, 127 Contact(s), 4 Row(s), Female, Right Angle, Press Fit Terminal, Receptacle, LEAD FREE; CategoryThe connector The connector; File Size237KB，3 Pages; ManufacturerAmphenol; Websitehttp://www.amphenol.com/; Environmental Compliance

Download Datasheet Parametric View All

51745-10010819C0LF Overview

Board Connector, 127 Contact(s), 4 Row(s), Female, Right Angle, Press Fit Terminal, Receptacle, LEAD FREE

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Amphenol
package instruction	LEAD FREE
Reach Compliance Code	compliant
Other features	TERMINAL PITCH FOR POWER CONTACTS: 6.35 MM
Body/casing type	RECEPTACLE
Connector type	BOARD CONNECTOR
Contact to complete cooperation	GOLD (30) OVER NICKEL (50)
Contact completed and terminated	TIN (78) OVER NICKEL (50)
Contact point gender	FEMALE
Contact material	COPPER ALLOY
DIN compliance	NO
Filter function	NO
IEC compliance	NO
JESD-609 code	e3
MIL compliance	NO
Manufacturer's serial number	51745
Mixed contacts	YES
Installation method	RIGHT ANGLE
Installation type	BOARD
Number of rows loaded	4
Options	GENERAL PURPOSE
Terminal pitch	2.54 mm
Termination type	PRESS FIT
Total number of contacts	127
UL Flammability Code	94V-0
Base Number Matches	1

PDM: Rev:H

STATUS:

Released

Printed: Oct 07, 2006

【Design Tools】MicroBlaze Support Example Xilkernel Example: This example details a Xilinx embedded system implemented using an embedded development kit, showcasing the features of the Xilkernel on a Microblaze soft processor. The hardware design used to demons...; GONGHCU FPGA/CPLD

Here are some Verilog books for you to read (continued): There is another book by Xia Yuwen that is too big to upload. I would like to contact you. The title of the book is "Verilog Digital System Design Tutorial [Xia Yuwen].rar"...; zhangkai0215 FPGA/CPLD

Circuit Question: I don't know what the device marked 3MS is in the circuit diagram?...; Benedict Integrated technical exchanges

18B20 Program: sbit DQ =P2^1; //Define the port according to the actual situation typedef unsigned char byte;typedef unsigned int word; //延时void delay(word useconds){ for(;useconds0;useconds--);} //Reset byte ow_res...; 破茧佼龙 MCU

FPGA development board schematic + example code: Yesterday I gave you two programs written in VHDL. Today I will share the Verilog routines. In fact, many large companies are currently developing with VHDL. It has strict syntax and standardized form...; super红红55 FPGA/CPLD

EEWORLD University Hall----Hands on Sensorless 1 (A): Hands on Sensorless 1 (A)：https://training.eeworld.com.cn/course/184...; dongcuipin Talking

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components