531MB1371M00DGR datasheet, PDF

Datasheet> All Categories > Passive components> oscillator> 531MB1371M00DGR

531MB1371M00DGR: DescriptionLVPECL Output Clock Oscillator, 1371MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

531MB1371M00DGR Overview

LVPECL Output Clock Oscillator, 1371MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531MB1371M00DGR Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
Reach Compliance Code	unknown
Other features	TAPE AND REEL
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	20%
JESD-609 code	e4
Manufacturer's serial number	531
Installation features	SURFACE MOUNT
Nominal operating frequency	1371 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVPECL
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)
Base Number Matches	1

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

Overview of Linear Optocoupler and Nonlinear Optocoupler Models

Audio DA converter circuit for multi-channel surround sound system

TPS92310 high power LED driver TPS92310 block diagram

Power switch integrated circuit water level control circuit

Small indoor duplex communication cordless telephone circuit diagram

555 household anti-theft and fire alarm circuit

Make your computer speak: During the New Year's Day, I accidentally saw the following code on the Internet, but I didn't know what it meant. I followed the method in the article, and finally my computer spoke. Now I will tell ...; zhangkai0215 Talking

Error when compiling ucgui+ucosii in keil: When I compile ucgui+ucosii in keil4, it finally appears compiling OS_Q.C...compiling OS_SEM.C...compiling OS_TASK.C...Source\uCOS-II\Source\OS_TASK.C(370): warning: #177-D: variable "self" was declar...; guozhiyang Microcontroller MCU

Dear heroes, please tell me about the TM4C123 timer synchronization problem: I want to make a program to measure the period of PWM square wave, using the period measurement method, using two timers of TM4C123 chip, one is used to capture the rising edge, which can record the t...; shiqiaocanxue Microcontroller MCU

Digital frequency meter: Please, send me [email]841418974@qq.com[/email]...; 想死你 Microcontroller MCU

Why is there no mouse cursor and no right button in the WINCE6.0 touch screen driver?: Experts, I use MS's layered driver model to write a touch screen driver. Currently, the driver can be calibrated, can drag, click, double-click, but can not generate the right button, and there is no ...; w19864h Embedded System

EEWORLD University Hall--Zuckerberg's version of Jarvis: [i=s]This post was last edited by Quantum Well on 2016-12-22 12:01[/i]Zuckerberg recently posted a video on his Facebook homepage, claiming that he has created the AI "Jarvis", which is Tony Stark's A...; 量子阱 Creative Market

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components