P
RELIMINARY
4 Megabit (512K x 8-Bit)
Low Voltage CMOS
33LV0408
33LV0408
Memory
Logic Diagram
F
EATURES
:
• R
AD
-P
AK
® Technology radiation-hardened
against natural space radiation
• 524,288 x 8 bit organization
· Total dose hardness:
- > 100 krad (Si), depending upon space mis-
sion
• Excellent Single Event Effect
·
- SEL
TH
: > 68 MeV/mg/cm
2
· - SEU
TH
: = 3 MeV/mg/cm
2
•
•
•
•
•
•
•
- SEU saturated cross section: 6E-9 cm
2
/bit
Package:
- 32-Pin R
AD
-P
AK
® flat pack
Fast access time:
- 15, 20, 25 ns maximum times available
Single 3.3 Volt power supply
Fully static operation
- No clock or refresh required
Three state outputs
TTL compatible inputs and outputs
Low power:
- Standby: 60 mA (TTL); 5 mA (CMOS)
D
ESCRIPTION
:
Maxwell Technologies’ 33LV0408 high-density 4
Megabit SRAM microcircuit features a greater than
100 krad (Si) total dose tolerance, depending upon
space mission. Using Maxwell’s radiation-hard-
ened R
AD
-P
AK
® packaging technology, the
33LV0408 realizes a high density, high perfor-
mance, and low power consumption. Its fully static
design eliminates the need for external clocks,
while the CMOS circuitry reduces power consump-
tion and provides higher reliability. The 33LV0408
is equipped with eight common input/output lines,
chip select and output enable, allowing for greater
system flexibility and eliminating bus contention.
The 33LV0408 features the same advanced 512K
x 8-bit SRAM, high-speed, and low-power demand
as the commercial counterpart.
Maxwell Technologies' patented R
AD
-P
AK
® packag-
ing technology incorporates radiation shielding in
the microcircuit package. It eliminates the need for
box shielding while providing the required radiation
shielding for a lifetime in orbit or space mission. In
a GEO orbit, R
AD
-P
AK
® provides greater than 100
krad (Si) radiation dose tolerance. This product is
available with screening up to Class S.
08.13.02 REV 1
All data sheets are subject to change without notice
1
(858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com
©2002 Maxwell Technologies
All rights reserved.
4 Megabit (512K x 8-Bit) Low Voltage SRAM
33LV0408
T
ABLE
1. P
INOUT
D
ESCRIPTION
P
IN
12-5, 27, 26, 23, 25, 4,
28, 3, 31, 2, 30, 1
29
22
24
13-15, 17-21
32
16
S
YMBOL
A0-A18
WE
CS
OE
I/O 1-I/O 8
V
CC
V
SS
D
ESCRIPTION
Address Inputs
Write Enable
Chip Select
Output Enable
Data Inputs/Outputs
Power (+5.0V)
Ground
T
ABLE
2. 33LV0408 A
BSOLUTE
M
AXIMUM
R
ATINGS
P
ARAMETER
Voltage on V
CC
supply relative to V
SS
Voltage on any pin relative to V
SS
Power Dissipation
Storage Temperature
Operating Temperature
S
YMBOL
V
CC
V
IN
, V
OUT
P
D
T
S
T
A
M
IN
-0.5
-0.5
--
-65
-55
M
AX
4.6
4.6
1.0
+150
+125
U
NIT
V
V
W
°
C
°
C
T
ABLE
3. D
ELTA
L
IMITS
P
ARAMETER
I
CC
I
SB
I
SB1
I
LI
V
ARIATION
±10% of stated vaule in Table 5
±10% of stated vaule in Table 5
±10% of stated vaule in Table 5
±10% of stated vaule in Table 5
08.13.02 REV 1
All data sheets are subject to change without notice
2
©2002 Maxwell Technologies
All rights reserved.
4 Megabit (512K x 8-Bit) Low Voltage SRAM
T
ABLE
4. 33LV0408 R
ECOMMENDED
O
PERATING
C
ONDITIONS
(V
CC
= 3.3 + 0.3V, T
A
= -55
TO
+125
°
C,
UNLESS OTHERWISE NOTED
)
P
ARAMETER
Supply Voltage
Ground
Input High Voltage
1
Input Low Voltage
2
1. V
IH
(max) = V
CC
+2.0V ac (pulse width < 10 ns) for I < 20 mA
2.
V
IL
(min) = -2.0V ac(pulse width < 10 ns) for I < 20 mA
S
YMBOL
V
CC
V
SS
V
IH
V
IL
M
IN
3.0
0
2.0
-0.3
2
33LV0408
M
AX
3.6
0
V
CC
+0.3
1
0.8
U
NIT
V
V
V
V
T
ABLE
5. 33LV0408 DC E
LECTRICAL
C
HARACTERISTICS
(V
CC
= 3.3V + 0.3V, T
A
= -55
TO
+125
°
C,
UNLESS OTHERWISE SPECIFIED
)
P
ARAMETER
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
Operating Current
-15
-20
-25
Standby Power
Supply Current
CMOS Standby Power
Supply Current
Input Capacitance
1
Output Capacitance
1
1. Guaranteed by design.
S
YMBOL
I
LI
I
LO
V
OL
V
OH
I
CC
C
ONDITION
V
IN
= V
SS
to V
CC
CS=V
IH
or OE=V
IH
or WE=V
IL
,
V
OUT
=V
SS
to V
CC
I
OL
= 8mA
I
OH
= -4mA
Min cycle, 100% Duty, CS=V
IL
, I
OUT
=0mA,
V
IN
= V
IH
or V
IL
S
UBGROUPS
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
--
--
--
1, 2, 3
1, 2, 3
--
--
?
180
170
60
5
mA
mA
M
IN
-2
-2
--
2.4
M
AX
2
2
0.4
--
U
NIT
µA
µA
V
V
mA
I
SB
I
SB1
CS = V
IH
, Min Cycle
CS > V
CC
- 0.2V, f = 0 MHz, V
IN
> V
CC
- 0.2V
or
V
IN
< 0.2V
V
IN
= 0V, f = 1MHz, T
A
= 25 °C
V
I/O
= 0V
C
IN
C
I/O
1, 2, 3
4, 5, 6
--
--
7
8
pF
pF
T
ABLE
6. 33LV0408 AC T
EST
C
ONDITIONS AND
C
HARACTERISTICS
(V
CC
= 3.3 + 0.3V, T
A
= -55
TO
+125
°
C,
UNLESS OTHERWISE NOTED
)
P
ARAMETER
Input Pulse Level
Output Timing Measurement Reference Level
Input Rise/Fall Time
08.13.02 REV 1
M
IN
0.0
--
--
T
YP
--
--
--
M
AX
3.0
1.5
3.0
U
NITS
V
V
ns
All data sheets are subject to change without notice
3
©2002 Maxwell Technologies
All rights reserved.
4 Megabit (512K x 8-Bit) Low Voltage SRAM
(V
CC
= 3.3 + 0.3V, T
A
= -55
TO
+125
°
C,
UNLESS OTHERWISE NOTED
)
P
ARAMETER
Input Timing Measurement Reference Level
M
IN
--
T
YP
--
33LV0408
M
AX
1.5
U
NITS
V
T
ABLE
6. 33LV0408 AC T
EST
C
ONDITIONS AND
C
HARACTERISTICS
T
ABLE
7. 33LV0408 AC C
HARACTERISTICS FOR
R
EAD
C
YCLE
(V
CC
= 3.3V + 0.3V, T
A
= -55
TO
+125
°
C,
UNLESS OTHERWISE SPECIFIED
)
P
ARAMETER
Read Cycle Time
-15
-20
-25
Address Access Time
-15
-20
-25
Chip Select Access Time
-15
-20
-25
Output Enable to Output Valid
-15
-20
-25
Chip Enable to Output in Low-Z
-15
-20
-25
Output Enable to Output in Low-Z
-15
-20
-25
Chip Deselect to Output in High-Z
-15
-20
-25
Output Disable to Output in High-Z
-15
-20
-25
Output Hold from Address Change
-15
-20
-25
t
AA
S
YMBOL
S
UBGROUPS
9, 10, 11
15
20
25
9, 10, 11
--
--
--
9, 10, 11
--
--
--
9, 10, 11
--
--
--
9, 10, 11
--
--
--
9, 10, 11
--
--
--
9, 10, 11
--
--
--
9, 10, 11
--
--
--
9, 10, 11
?
3
5
--
--
--
--
--
--
?
?
?
--
--
--
ns
?
?
?
--
--
--
ns
0
0
0
--
--
--
ns
3
3
3
--
--
--
ns
--
--
--
7
10
12
ns
--
--
--
15
20
25
--
--
--
15
20
25
ns
--
--
--
--
--
--
ns
M
IN
T
YP
M
AX
U
NIT
ns
t
CO
t
OE
t
LZ
ns
t
OLZ
t
HZ
t
OHZ
t
OH
08.13.02 REV 1
All data sheets are subject to change without notice
4
©2002 Maxwell Technologies
All rights reserved.
4 Megabit (512K x 8-Bit) Low Voltage SRAM
T
ABLE
7. 33LV0408 AC C
HARACTERISTICS FOR
R
EAD
C
YCLE
(V
CC
= 3.3V + 0.3V, T
A
= -55
TO
+125
°
C,
UNLESS OTHERWISE SPECIFIED
)
P
ARAMETER
Chip Select to Power Up Time
-15
-20
-25
Chip Select to Power Down Time
-15
-20
-25
S
YMBOL
t
PU
S
UBGROUPS
9, 10, 11
--
--
--
9, 10, 11
--
--
--
?
?
?
0
0
0
M
IN
T
YP
33LV0408
M
AX
--
--
--
ns
--
--
--
U
NIT
ns
t
PD
T
ABLE
8. 33LV0408 F
UNCTIONAL
D
ESCRIPTION
CS
H
L
L
L
1. X = don’t care.
WE
X
1
H
H
L
OE
X
1
H
L
X
1
M
ODE
Not Select
Output Disable
Read
Write
I/O P
IN
High-Z
High-Z
D
OUT
D
IN
S
UPPLY
C
URRENT
I
SB
, I
SB1
I
CC
I
CC
I
CC
Subgroups
T
ABLE
9. 33LV0408 AC C
HARACTERISTICS FOR
W
RITE
C
YCLE
(V
CC
= 3.3V + 0.3V, T
A
= -55
TO
+125
°
C,
UNLESS OTHERWISE SPECIFIED
)
P
ARAMETER
Write Cycle Time
-20
-25
-30
Chip Select to End of Write
-20
-25
-30
Address Setup Time
-20
-25
-30
Address Valid to End of Write
-20
-25
-30
S
UBGROUPS
9, 10, 11
S
YMBOL
t
WC
M
IN
20
25
30
?
14
15
0
0
0
?
14
15
T
YP
--
--
--
--
--
--
--
--
--
--
--
--
M
AX
--
--
--
ns
--
--
--
ns
--
--
--
ns
--
--
--
U
NIT
ns
9, 10, 11
t
CW
9, 10, 11
t
AS
9, 10, 11
t
AW
08.13.02 REV 1
All data sheets are subject to change without notice
5
©2002 Maxwell Technologies
All rights reserved.
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