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AD667–SPECIFICATIONS
Model
Min
DIGITAL INPUTS
Resolution
Logic Levels (TTL, Compatible, T
MIN
–T
MAX
)
1
V
IH
(Logic “l’’)
V
IL
(Logic “0”)
I
IH
(V
IH
= 5.5 V)
I
IL
(V
IL
= 0.8 V)
TRANSFER CHARACTERISTICS
ACCURACY
Linearity Error @ +25°C
T
A
= T
MIN
to T
MAX
Differential Linearity Error @ +25°C
T
A
= T
MIN
to T
MAX
Gain Error
2
Unipolar Offset Error
2
Bipolar Zero
2
DRIFT
Differential Linearity
Gain (Full Scale) T
A
= 25°C to T
MIN
or T
MAX
Unipolar Offset T
A
= –25°C to T
MIN
or T
MAX
Bipolar Zero T
A
= 25°C to T
MIN
or T
MAX
CONVERSION SPEED
Settling Time to
±
0.01% of FSR for
FSR Change (2 kΩ 500 pF Load)
with 10 kΩ Feedback
with 5 kΩ Feedback
For LSB Change
Slew Rate
ANALOG OUTPUT
Ranges
4
Output Current
Output Impedance (DC)
Short Circuit Current
REFERENCE OUTPUT
External Current
POWER SUPPLY SENSITIVITY
V
CC
= +11.4 V to +16.5 V dc
V
EE
= –11.4 V to –16.5 V dc
POWER SUPPLY REQUIREMENTS
Rated Voltages
Range
4
Supply Current
+11.4 V to +16.5 V dc
–11.4 V to –16.5 V dc
TEMPERATURE RANGE
Specification
Storage
NOTES
1
2
(@ T
A
= +25 C,
AD667J
Typ
12 V,
Max
15 V power supplies unless otherwise noted)
Min
AD667K
Typ
Max
Units
12
+2.0
0
3
1
+5.5
+0.8
10
5
+2.0
0
3
1
12
+5.5
+0.8
10
5
Bits
V
V
µA
µA
+1/4
1/2
±
1/2
3/4
±
1/2
3/4
Monotonicity Guaranteed
±
0.1
0.2
±
1
2
±
0.05
0.1
±
2
±
5
±
1
±
5
±
1/8
1/4
±
1/4
1/2
±
1/4
1/2
Monotonicity Guaranteed
±
0.1
0.2
±
1
2
±
0.05
0.1
±
2
±
5
LSB
LSB
LSB
LSB
% FSR
3
LSB
% of FSR
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
±
30
±
3
±
10
±
15
±
3
±
10
3
2
1
10
±
2.5,
±
5,
±
10,
+5, +10
0.05
4
3
10
3
2
1
4
3
µs
µs
µs
V/µs
V
mA
Ω
mA
V
mA
ppm of FS/%
ppm of FS/%
V
V
mA
mA
°C
°C
±
5
±
5
40
±
2.5,
±
5,
±
10,
+5, +10
0.05
40
9.90
0.1
10.00
1.0
5
5
±
12,
±
15
10.10
9.90
0.1
10.00
1.0
5
5
±
12,
±
15
10.10
10
10
10
10
11.4
8
20
0
–65
16.5
12
25
+70
+125
11.4
8
20
0
–65
16.5
12
25
+70
+125
The digital input specifications are 100% tested at +25°C, and guaranteed but not tested over the full temperature range.
Adjustable to zero.
3
FSR means “Full-Scale Range” and is 20 V for
±
10 V range and 10 V for the
±
5 V range.
4
A minimum power supply of
±
12.5 V is required for a
±
10 V full-scale output and
±
11.4 V is required for all other voltage ranges.
Specifications subject to change without notice.
Specifications shown in
boldface
are tested on all production units at final electrical
test. Results from those tests are used to calculate outgoing quality levels. All min and
max specifications are guaranteed, although only those shown in boldface are tested
on all production units.
ABSOLUTE MAXIMUM RATINGS
TIMING SPECIFICATIONS
(All Models, T
A
= +25°C, V
CC
= +12 V or +15 V, V
EE
= –12 V or –15 V)
Symbol
t
DC
t
AC
t
CP
t
DH
t
SETT
Parameter
Data Valid to End of
CS
Address Valid to End of
CS
CS
Pulse Width
Data Hold Time
Output Voltage Settling Time
Min
50
100
100
0
–
Typ
–
_
–
–
2
Max
–
_
–
–
4
ns
ns
ns
ns
µs
V
CC
to Power Ground . . . . . . . . . . . . . . . . . . . . . 0 V to +18 V
V
EE
to Power Ground . . . . . . . . . . . . . . . . . . . . . 0 V to –18 V
Digital Inputs (Pins 11–15, 17–28)
to Power Ground . . . . . . . . . . . . . . . . . . . . –1.0 V to +7.0 V
Ref In to Reference Ground . . . . . . . . . . . . . . . . . . . . . .
±
12 V
Bipolar Offset to Reference Ground . . . . . . . . . . . . . . . .
±
12 V
10 V Span R to Reference Ground . . . . . . . . . . . . . . . . .
±
12 V
20 V Span R to Reference Ground . . . . . . . . . . . . . . . . .
±
24 V
Ref Out, V
OUT
(Pins 6, 9) . . Indefinite Short to Power Ground
. . . . . . . . . . . . . . . . . . . . . . . . . . . Momentary Short to V
CC
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mW
–2–
REV. A
AD667
Model
AD667A
Min
Typ
Max
Min
AD667B
Typ
Max
Min
AD667S
Typ
Max
Units
DIGITAL INPUTS
Resolution
Logic Levels (TTL, Compatible, T
MIN
–T
MAX
)
1
V
IH
(Logic “l’’)
V
IL
(Logic “0”)
I
IH
(V
IH
= 5.5 V)
I
IL
(V
IL
= 0.8 V)
TRANSFER CHARACTERISTICS
ACCURACY
Linearity Error @ +25°C
T
A
= T
MIN
to T
MAX
Differential Linearity Error @ +25°C
T
A
= T
MIN
to T
MAX
Gain Error
2
Unipolar Offset Error
2
Bipolar Zero
2
DRIFT
Differential Linearity
Gain (Full Scale) T
A
= 25°C to T
MIN
or T
MAX
Unipolar Offset T
A
= 25°C to T
MIN
or T
MAX
Bipolar Zero T
A
= 25°C to T
MIN
or T
MAX
CONVERSION SPEED
Settling Time to
±
0.01% of FSR for
FSR Change (2 kΩ 500 pF Load)
with 10 kΩ Feedback
with 5 kΩ Feedback
For LSB Change
Slew Rate
ANALOG OUTPUT
Ranges
4
Output Current
Output Impedance (DC)
Short Circuit Current
REFERENCE OUTPUT
External Current
POWER SUPPLY SENSITIVITY
V
CC
= +11.4 V to +16.5 V dc
V
EE
= –11.4 V to –16.5 V dc
POWER SUPPLY REQUIREMENTS
Rated Voltages
Range
4
Supply Current
+11.4 V to +16.5 V dc
–11.4 V to –16.5 V dc
TEMPERATURE RANGE
Specification
Storage
±
5
12
+2.0
0
3
1
+5.5
+0.8
10
5
+2.0
0
3
1
12
+5.5
+0.8
10
5
+2.0
0
3
1
12
+5.5
+0.7
10
5
Bits
V
V
µA
µA
+1/4
1/2
±
1/2
3/4
±
1/2
3/4
Monotonicity Guaranteed
±
0.1
0.2
±
1
2
±
0.05
0.1
±
2
±
5
±
1
±
5
±
1/8
1/4
±
1/4
1/2
±
1/4
1/2
Monotonicity Guaranteed
±
0.1
0.2
±
1
2
±
0.05
0.1
±
2
±
5
±
1/8
1/2
±
1/8
3/4
±
1/4
3/4
Monotonicity Guaranteed
±
0.1
0.2
±
1
2
±
0.05
0.1
±
2
±
15
LSB
LSB
LSB
LSB
% FSR
3
LSB
% of FSR
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
±
30
±
3
±
10
±
15
±
3
±
10
30
3
10
3
2
1
10
4
3
10
3
2
1
4
3
10
3
2
1
4
3
µs
µs
µs
V/µs
V
mA
Ω
mA
V
mA
ppm of FS/%
ppm of FS/%
V
V
mA
mA
°C
°C
±
2.5,
±
5,
±
10,
+5, +10
0.05
40
±
5
±
2.5,
±
5,
±
10,
+5, +10
0.05
40
±
5
±
2.5,
±
5,
±
10,
+5, +10
0.05
40
9.90
0.1
10.00
1.0
5
5
±
12,
±
15
10.10
9.90
0.1
10.00
1.0
5
5
±
12,
±
15
10.10
9.90
1.0
10.00
10.10
10
10
10
10
5
5
±
12,
±
15
10
10
11.4
8
20
–25
–65
16.5
12
25
+85
+150
11.4
8
20
–25
–65
16.5
12
25
+85
+150
11.4
8
20
–55
–65
16.5
12
25
+125
+150
TIMING DIAGRAMS
WRITE CYCLE #1
WRITE CYCLE #2
(Load Second Rank from First Rank; A2, A1, A0 = 1)
(Load First Rank from Data Bus; A3 = 1)
REV. A
–3–
AD667
PIN CONNECTIONS
PLCC, LCC
DIP
ORDERING GUIDE
Temperature
Range— C
0 to +70
0 to +70
0 to +70
0 to +70
25 to +85
–25 to +85
–55 to +125
–55 to +125
–55 to +125
Linearity
Gain
Error Max TC Max
@ +25 C
ppm/ C Package Option
2
±
1/2 LSB
±
1/2 LSB
±
1/4 LSB
±
1/4 LSB
±
1/2 LSB
±
1/4 LSB
±
1/2 LSB
±
1/2 LSB
*
30
30
15
15
30
15
30
30
*
Plastic DIP (N-28)
PLCC (P-28A)
Plastic DIP (N-28)
PLCC (P-28A)
Ceramic DIP (D-28)
Ceramic DIP (D-28)
Ceramic DIP (D-28)
LCC (E-28A)
*
Model
l
AD667JN
AD667JP
AD667KN
AD667KP
AD667AD
AD667BD
AD667SD
AD667SE
AD667/883B
from the ideal analog output (a straight line drawn from 0 to FS
– 1 LSB) for any bit combination. The AD667 is laser trimmed
to 1/4 LSB (0.006% of FS) maximum error at +25°C for the K
and B versions and 1/2 LSB for the J, A and S versions.
MONOTONICITY: A DAC is said to be monotonic if the
output either increases or remains constant for increasing digital
inputs such that the output will always be a nondecreasing func-
tion of input. All versions of the AD667 are monotonic over
their full operating temperature range.
DIFFERENTIAL NONLINEARITY: Monotonic behavior re-
quires that the differential linearity error be less than 1 LSB
both at +25°C and over the temperature range of interest. Dif-
ferential nonlinearity is the measure of the variation in analog
value, normalized to full scale, associated with a 1 LSB change
in digital input code. For example, for a 10 volt full-scale out-
put, a change of 1 LSB in digital input code should result in a
2.44 mV change in the analog output (1 LSB = 10 V
×
1/4096 =
2.44 mV). If in actual use, however, a 1 LSB change in the
input code results in a change of only 0.61 mV (1/4 LSB) in
analog output, the differential linearity error would be –1.83 mV,
or –3/4 LSB. The AD667K and B grades have a max differential
linearity error of 1/2 LSB, which specifies that every step will be
at least 1/2 LSB and at most 1 1/2 LSB.
NOTES
*Refer to AD667/883B military data sheet.
1
For details on grade and package offerings screened in accordance with MIL-STD-
883, refer to the Analog Devices Military Products Databook or current AD667/
883B data sheet.
2
D = Ceramic DIP; E = Leadless Ceramic Chip Carrier; N = Plastic DIP;
P = Plastic Leaded Chip.
THE AD667 OFFERS TRUE 12-BIT PERFORMANCE
OVER THE FULL TEMPERATURE RANGE
LINEARITY ERROR: Analog Devices defines linearity error as
the maximum deviation of the actual, adjusted DAC output
Table I. Output Voltage Range Connections
Output
Range
±
10 V
±
5 V
±
2.5 V
0 V to +10 V
0 V to +5 V
Digital
Input Codes
Offset Binary
Offset Binary
Offset Binary
Straight Binary
Straight Binary
Connect
Pin 9 to
1
1 and 2
2
1 and 2
2
Connect
Pin 1 to
9
2 and 9
3
2 and 9
3
Connect
Pin 2 to
NC
1 and 9
9
1 and 9
9
–4–
Connect
Pin 4 to
6 (Through 50
Ω
Fixed or 100
Ω
Trim Resistor)
6 (Through 50
Ω
Fixed or 100
Ω
Trim Resistor)
6 (Through 50
Ω
Fixed or 100
Ω
Trim Resistor)
5 (or Optional Trim—See Figure 2)
5 (or Optional Trim—See Figure 2)
REV. A
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