MB90F952JDS/F952MDS
MB90V950AJAS/V950AMAS
F
2
MC-16LX MB90950 Series
16-bit Microcontrollers
The MB90950-series with 2 FULL-CAN interfaces and Flash ROM is especially designed for automotive and other industrial applica-
tions. Its main feature are the on-board CAN Interfaces, which conform to V2.0 Part A and Part B, while supporting a very flexible
message buffer scheme and so offering more functions than a normal FULL-CAN approach. With the new 0.18
m CMOS technology,
Fujitsu now offers on-chip Flash ROM program memory 256 Kbytes.
The power to the MCU core (1.8 V) is supplied by a built-in regulator circuit, giving these microcontrollers superior performance in
terms of power consumption and tolerance to EMI.
Features
CPU
■
■
Instruction system best suited to controller
- Wide choice of data types (bit, byte, word, and long word)
- Wide choice of addressing modes (23 types)
- Enhanced functionality with signed multiply and divide instruc-
tions and the RETI instruction
- Enhanced high-precision computing with 32-bit accumulator
Instruction system compatible with high-level language (C
language) and multitask
- Employing system stack pointer
- Various enhanced pointer indirect instructions
- Barrel shift instructions
Increased processing speed
4-byte instruction queue
UART (LIN/SCI): 7 channels
- Equipped with full-duplex double buffer
- Clock-asynchronous or clock-synchronous serial trans-
mission is available
I
2
C interface: 2 channels
Up to 400 kbps transfer rate
Powerful 8-level, 34-condition interrupt feature
Up to 16 external interrupts are supported
Automatic data transfer function independent of CPU
Expanded intelligent I/O service function (EI
2
OS): up to 16
channels
DMA function: up to 16 channels
General-purpose input/output port (CMOS output) : 82 ports
Resolution is selectable between 8-bit and 10-bit.
Activation by external trigger input is allowed.
Conversion time: 3
s (at 32-MHz machine clock, including
sampling time)
8-bit D/A converter: 2 channels
Program patch function
Detects address matches against 6 address pointers
Timer
■
■
■
■
■
Time-base timer, watch timer, watchdog timer: 1 channel
8/16-bit PPG timer: 8-bit
16 channels, or 16-bit
8 channels
16-bit reload timer: 4 channels
16-bit input/output timer
- 16-bit free-run timer: 2 channels
(FRT0: ICU 0/1/2/3, OCU 0/1/2/3, FRT1: ICU 4/5/6/7, OCU
4/5/6/7)
- 16-bit input capture: (ICU): 8 channels
- 16-bit output compare: (OCU): 8 channels
2 channels
Compliant with Ver2.0A and Ver2.0B CAN specifications
16 built-in message buffers
CAN wake-up function
Sleep mode (a mode that halts CPU operating clock)
Timebase timer mode (a mode where only the oscillation clock,
sub clock, timebase timer and watch timer operate)
Watch mode (a mode that operates sub clock and clock timer
only)
Stop mode (a mode that stops oscillation clock and sub clock)
CPU intermittent operation mode
■
Serial interface
■
FULL-CAN controller
■
■
■
■
■
Interrupt controller
■
■
■
Low power consumption (standby) mode
■
■
■
■
■
I/O ports
■
8/10-bit A/D converter: 24 channels
■
■
Technology
0.18
m CMOS technology
Cypress Semiconductor Corporation
Document Number: 002-04500 Rev. *A
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised April 13, 2016
MB90950 Series
Contents
Product Lineup ................................................................ 3
Pin Assignments .............................................................. 6
Pin Description ................................................................ 8
I/O Circuit Types ............................................................. 16
Handling Devices ............................................................ 22
Block Diagrams .............................................................. 25
Memory Map .................................................................... 27
I/O Map ........................................................................... 28
CAN Controllers .............................................................. 40
Interrupt Factors, Interrupt Vectors,
Interrupt Control Register .............................................. 47
Electrical Characteristics ............................................... 49
Absolute Maximum Ratings ....................................... 49
Recommended Operating Conditions ....................... 51
DC Characteristics .................................................... 52
AC Characteristics ..................................................... 55
Clock Timing .............................................................. 55
Reset Standby Input .................................................. 57
Power On Reset ........................................................ 58
Clock Output Timing .................................................. 58
Bus Timing (Read) .................................................... 59
Bus Timing (Write) ..................................................... 61
Ready Input Timing ................................................... 63
Hold Timing ............................................................... 64
UART ......................................................................... 65
rigger Input Timing .................................................... 70
Timer Related Resource Input Timing ....................... 71
Timer Related Resource Output Timing .................... 71
Low voltage detection ................................................ 72
I2C Timing ................................................................. 73
CAN PLL cycle jitter .................................................. 74
A/D Converter ............................................................ 75
Definition of A/D Converter Terms ........................... 76
Notes on A/D Converter Section ............................... 78
Flash Memory Program/Erase Characteristics ......... 80
D/A Converter
...................................................................80
Ordering Information ...................................................... 81
Package Dimensions ...................................................... 82
Major Changes................................................................ 84
Document Number: 002-04500 Rev. *A
Page 2 of 85
MB90950 Series
1. Product Lineup
Part Number
MB90V950AJAS
Parameter
Type
CPU
System clock
ROM
RAM
Emulator-specific power
supply*
1
FPGA data*
2
Adaptor board*
2
Clock supervisor
Clock calibration unit
Low-voltage/CPU opera-
tion detection reset
Technology
Operating
voltage range
Operating ambient tem-
perature
Package
Yes
Yes
No
(CPU operation
detection reset only)
0.35
m
CMOS with built-in
power supply regulator
5 V
10
Evaluation products
F
2
MC-16LX CPU
On-chip PLL clock multiplier (
1,
2,
3,
4,
6,
8, 1/2 when PLL stops)
Minimum instruction execution time : 31.25 ns (4 MHz osc. PLL
8)
External
30 Kbytes
Yes
Rev 050617
MB2147-20 Rev.04C or later
No
No
No
Yes
Yes
Yes
Main 256 Kbytes
Satellite 32 Kbytes
16 Kbytes
Flash memory products
MB90V950AMAS
MB90F952JDS
MB90F952MDS
No
No
No
0.18
m
CMOS with built-in power supply regulator
Flash memory with Charge pump for programming volt-
age
3.0 V to 5.5 V
4.0 V to 5.5 V
4.5 V to 5.5 V
: When normal operating
: When Flash programming
: When using the external bus
40C
to
105C
QFP-100, LQFP-100
7 channels
PGA-299
UART
I
2
C (400 kbps)
A/D Converter
16-bit Reload Timer
(4 channels)
Wide range of baud rate settings using a dedicated reload timer
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality working either as master or slave LIN device
2 channels
24 input channels
10-bit or 8-bit resolution
Conversion time : Min 3
s
include sample time (per one channel)
Operation clock frequency : fsys/2
1
, fsys/2
3
, fsys/2
5
(fsys
½
Machine clock frequency)
Supports External Event Count function
Document Number: 002-04500 Rev. *A
Page 3 of 85
MB90950 Series
Part Number
MB90V950AJAS
Parameter
16-bit I/O Timer
(2 channels)
Generates an interrupt signal on overflow
Supports Timer Clear when the output compare finds a match
Operation clock freq. : fsys, fsys/2
1
, fsys/2
2
, fsys/2
3
, fsys/2
4
, fsys/2
5
, fsys/2
6
, fsys/2
7
(fsys
½
Machine clock freq.)
I/O Timer 0 (clock input FRCK0) corresponds to ICU0/1/2/3, OCU 0/1/2/3
I/O Timer 1 (clock input FRCK1) corresponds to ICU4/5/6/7, OCU 4/5/6/7
Generates an interrupt signal when one of the 16-bit I/O timer matches the output compare register
A pair of compare registers can be used to generate an output signal.
Holds free-run timer on rising edge, falling edge or rising & falling edge
Signals an interrupt upon external event
8 channels (16-bit) /16 channels (8-bit)
Sixteen 8-bit reload counters
Sixteen 8-bit reload registers for L pulse width
Sixteen 8-bit reload registers for H pulse width
Supports 8-bit and 16-bit operation modes
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as
8-bit prescaler plus 8-bit reload counter
Operating clock freq. : fsys, fsys/2
1
, fsys/2
2
, fsys/2
3
, fsys/2
4
or 128
s@fosc ½
4 MHz
(fsys
½
Machine clock frequency, fosc
½
Oscillation clock frequency)
3 channels
Conforms to CAN Specification Version 2.0 Part A and B
Automatic re-transmission in case of error
Automatic transmission in response to Remote Frames
Prioritized 16 message buffers for data and ID’s
Supports multiple messages
Flexible configuration of acceptance filtering :
Full bit compare/Full bit mask/Two partial bit masks
Supports up to 1 Mbps
Can be used rising edge, falling edge, starting up by H/L level input, external interrupt,
expanded intelligent I/O services (EI
2
OS) and DMA
2 channels
Yes
No
Yes
No
2 channels
MB90V950AMAS
MB90F952JDS
MB90F952MDS
16-bit Output
Compare
(8 channels)
16-bit Input Capture
(8 channels)
8/16-bit
Programmable Pulse
Generator
CAN Interface
External Interrupt
(16 channels)
D/A converter
Sub clock
I/O Ports
Virtually all external pins can be used as general purpose I/O port
All ports are push-pull outputs
Bit-wise settable as input/output or peripheral signal
Can be configured 8 as CMOS schmitt trigger/ automotive inputs (in blocks of 8 pins)
TTL input level settable for external bus (32-pin only for external bus)
Document Number: 002-04500 Rev. *A
Page 4 of 85
MB90950 Series
Part Number
MB90V950AJAS
Parameter
Supports automatic programming, Embedded Algo-
rithm
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Boot block configuration
Erase can be performed on each block
Block protection with external programming voltage
Flash Security Feature for protecting the content of the
Flash
MB90V950AMAS
MB90F952JDS
MB90F952MDS
Flash Memory
*1 : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used.
Please refer to the Emulator hardware manual for details.
*2 : Customers considering the use of other FPGA data and the adaptor boards should consult with sales representatives.
Document Number: 002-04500 Rev. *A
Page 5 of 85
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