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74HC112; 74HCT112
Dual JK flip-flop with set and reset; negative-edge trigger
Rev. 3 — 9 August 2016
Product data sheet
1. General description
The 74HC112; 74HCT112 is a dual negative-edge triggered JK flip-flop. It features
individual J and K inputs, clock (nCP) set (nSD) and reset (nRD) inputs. It also has
complementary nQ and nQ outputs. The set and reset are asynchronous active LOW
inputs and operate independently of the clock input. The J and K inputs control the state
changes of the flip-flops as described in the mode select function table. The J and K
inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for
predictable operation. Inputs include clamp diodes that enable the use of current limiting
resistors to interface inputs to voltages in excess of V
CC
.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock
rise and fall times.
2. Features and benefits
Input levels:
For 74HC112: CMOS level
For 74HCT112: TTL level
Asynchronous set and reset
Specified in compliance with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from
40 C
to +85
C
and from
40 C
to +125
C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC112D
74HCT112D
74HC112DB
74HCT112DB
74HC112PW
74HCT112PW
40 C
to +125
C
40 C
to +125
C
SSOP16
plastic shrink small outline package; 16 leads; body width
5.3 mm
SOT338-1
SOT403-1
40 C
to +125
C
Name
SO16
Description
Version
plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
Type number
TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
NXP Semiconductors
74HC112; 74HCT112
Dual JK flip-flop with set and reset; negative-edge trigger
4. Functional diagram
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram (one flip-flop)
74HC_HCT112
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 3 — 9 August 2016
2 of 20
NXP Semiconductors
74HC112; 74HCT112
Dual JK flip-flop with set and reset; negative-edge trigger
5. Pinning information
5.1 Pinning
Fig 4.
Pin configuration for SO16
Fig 5.
Pin configuration for (T)SSOP16
5.2 Pin description
Table 2.
Symbol
1CP, 2CP
1K, 2K
1J, 2J
1SD, 2SD
1Q, 2Q
1Q, 2Q
GND
1RD, 2RD
V
CC
Pin description
Pin
1, 13
2, 12
3, 11
4, 10
5, 9
6, 7
8
15, 14
16
Description
clock input (HIGH-to-LOW; edge-triggered)
data input
data input
set input (active LOW)
true flip-flop output
complement flip-flop output
ground (0 V)
reset input (active LOW)
supply voltage
74HC_HCT112
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 3 — 9 August 2016
3 of 20
NXP Semiconductors
74HC112; 74HCT112
Dual JK flip-flop with set and reset; negative-edge trigger
6. Functional description
Table 3.
Function selection
[1]
Input
nSD
Asynchronous set
Asynchronous reset
Undetermined
Toggle
Load 0 (reset)
Load 1 (set)
Hold no change
[1]
Operating modes
Output
nRD
H
L
L
H
H
H
H
nCP
X
X
X
nJ
X
X
X
h
l
h
l
nK
X
X
X
h
h
l
l
nQ
H
L
H
q
L
H
q
nQ
L
H
L
q
H
L
q
L
H
L
H
H
H
H
If nSD and nRD simultaneously go from LOW-to-HIGH, the output states are unpredictable.
H = HIGH voltage level
h = HIGH voltage level one set-up time before the HIGH-to-LOW clock transition
L = LOW voltage level
l = LOW voltage level one set-up time before the HIGH-to-LOW clock transition
q = lowercase letters indicate the state of the referenced output one set-up time before the HIGH-to-LOW clock transition
X = don’t care
= HIGH-to-LOW clock transition
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
0.5
V < V
O
< V
CC
+ 0.5 V
Min
0.5
-
-
-
-
50
65
Max
+7
20
20
25
+50
-
+150
500
Unit
V
mA
mA
mA
mA
mA
C
mW
SO16 and (T)SSOP16 packages
[1]
-
For SO16 packages: above 70
C,
the value of P
tot
derates linearly with 8 mW/K.
For (T)SSOP16 packages: above 60
C,
the value of P
tot
derates linearly with 5.5 mW/K.
74HC_HCT112
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 3 — 9 August 2016
4 of 20
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