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74LV08PW

Description
AND Gate
Categorylogic    logic   
File Size502KB,14 Pages
ManufacturerNexperia
Websitehttps://www.nexperia.com
Environmental Compliance
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74LV08PW Overview

AND Gate

74LV08PW Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerNexperia
package instructionTSSOP,
Reach Compliance Codecompliant
Samacsys DescriptionNXP 74LV08PW, Quad 2-Input AND Logic Gate, 1 → 5.5 V, 14-Pin TSSOP
seriesLV/LV-A/LVX/H
JESD-30 codeR-PDSO-G14
length5 mm
Logic integrated circuit typeAND GATE
Humidity sensitivity level1
Number of functions4
Number of entries2
Number of terminals14
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
propagation delay (tpd)33 ns
Maximum seat height1.1 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)1 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal surfaceNOT SPECIFIED
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width4.4 mm
Important notice
Dear Customer,
On 7 February 2017 the former NXP Standard Product business became a new company with the
tradename
Nexperia.
Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS
semiconductors with its focus on the automotive, industrial, computing, consumer and wearable
application markets
In data sheets and application notes which still contain NXP or Philips Semiconductors references, use
the references to Nexperia, as shown below.
Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/,
use
http://www.nexperia.com
Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use
salesaddresses@nexperia.com
(email)
Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on
the version, as shown below:
- © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights
reserved
Should be replaced with:
-
© Nexperia B.V. (year). All rights reserved.
If you have any questions related to the data sheet, please contact our nearest sales office via e-mail
or telephone (details via
salesaddresses@nexperia.com).
Thank you for your cooperation and
understanding,
Kind regards,
Team Nexperia

74LV08PW Related Products

74LV08PW 74LV08D-T 74LV08DB-T 74LV08D 74LV08DB 74LV08PW-T
Description AND Gate AND Gate AND Gate AND Gate AND Gate AND Gate
Maker Nexperia Nexperia Nexperia Nexperia Nexperia Nexperia
package instruction TSSOP, SOP, SSOP, SOP, SSOP, TSSOP,
Reach Compliance Code compliant compliant compliant compliant compliant compliant
series LV/LV-A/LVX/H LV/LV-A/LVX/H LV/LV-A/LVX/H LV/LV-A/LVX/H LV/LV-A/LVX/H LV/LV-A/LVX/H
JESD-30 code R-PDSO-G14 R-PDSO-G14 R-PDSO-G14 R-PDSO-G14 R-PDSO-G14 R-PDSO-G14
length 5 mm 8.65 mm 6.2 mm 8.65 mm 6.2 mm 5 mm
Logic integrated circuit type AND GATE AND GATE AND GATE AND GATE AND GATE AND GATE
Number of functions 4 4 4 4 4 4
Number of entries 2 2 2 2 2 2
Number of terminals 14 14 14 14 14 14
Maximum operating temperature 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C
Minimum operating temperature -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TSSOP SOP SSOP SOP SSOP TSSOP
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
propagation delay (tpd) 33 ns 33 ns 33 ns 33 ns 33 ns 33 ns
Maximum seat height 1.1 mm 1.75 mm 2 mm 1.75 mm 2 mm 1.1 mm
Maximum supply voltage (Vsup) 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V
Minimum supply voltage (Vsup) 1 V 1 V 1 V 1 V 1 V 1 V
Nominal supply voltage (Vsup) 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
surface mount YES YES YES YES YES YES
technology CMOS CMOS CMOS CMOS CMOS CMOS
Temperature level AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE
Terminal form GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING
Terminal pitch 0.65 mm 1.27 mm 0.65 mm 1.27 mm 0.65 mm 0.65 mm
Terminal location DUAL DUAL DUAL DUAL DUAL DUAL
width 4.4 mm 3.9 mm 5.3 mm 3.9 mm 5.3 mm 4.4 mm
Is it Rohs certified? conform to conform to conform to conform to conform to -
Peak Reflow Temperature (Celsius) 260 NOT SPECIFIED NOT SPECIFIED 260 260 -
Terminal surface NOT SPECIFIED Nickel/Palladium/Gold (Ni/Pd/Au) - Nickel/Palladium/Gold (Ni/Pd/Au) NOT SPECIFIED -
Maximum time at peak reflow temperature 30 NOT SPECIFIED NOT SPECIFIED 30 30 -

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