HM534251B Series
262144-word
×
4-bit Multiport CMOS Video RAM
Description
The HM534251B is a 1-Mbit multiport video RAM equipped with a 256-kword
×
4-bit dynamic RAM and a
512-word
×
4-bit SAM (serial access memory). Its RAM and SAM operate independently and
asynchronously. It can transfer data between RAM and SAM and has write mask function.
Features
•
Multiport organization
Asynchronous and simultaneous operation of RAM and SAM capability
RAM: 256-kword
×
4-bit
SAM: 512-word
×
4-bit
•
Access time
RAM: 60 ns/70 ns/80 ns/100 ns max
SAM: 20 ns/22 ns/25 ns/25 ns max
•
Cycle time
RAM: 125 ns/135 ns/150 ns/180 ns min
SAM: 25 ns/25 ns/30 ns/30 ns min
•
Low power
Active
RAM: 413 mW max
SAM: 275 mW max
Standby
38.5 mW max
•
High-speed page mode capability
•
Mask write mode capability
•
Bidirectional data transfer cycle between RAM and SAM capability
•
Real time read transfer cycle capability
•
3 variations of refresh (8 ms/512 cycles)
RAS-only
refresh
CAS-before-RAS
refresh
Hidden refresh
•
TTL compatible
HM534251B Series
Pin Functions
RAS
(input pin):
RAS
is a basic RAM signal. It is active in low level and standby in high level. Row
address and signals as shown in table 1 are input at the falling edge of
RAS.
The input level of these signals
determine the operation cycle of the HM534251B.
Table 1. Operation Cycles of the HM534251B
Input Level At The Falling Edge Of
RAS
CAS
L
H
H
H
H
H
DT/OE
X
L
L
L
H
H
WE
X
L
L
H
L
H
SE
X
L
H
X
X
X
Operation Mode
CBR refresh
Write transfer
Pseudo transfer
Read transfer
Read/mask write
Read/write
Note: X : Don’t care.
CAS
(input pin):
Column address is fetched into chip at the falling edge of
CAS. CAS
controls output
impedance of I/O in RAM.
A0–A8 (input pins):
Row address is determined by A0–A8 level at the falling edge of
RAS.
Column
address is determined by A0-A8 level at the falling edge of
CAS.
In transfer cycles, row address is the
address on the word line which transfers data with SAM data register, and column address is the SAM start
address after transfer.
WE
(input pin):
WE
pin has two functions at the falling edge of
RAS
and after. When
WE
is low at the
falling edge of
RAS,
the HM534251B turns to mask write mode. According to the I/O level at the time, write
on each I/O can be masked. (WE level at the falling edge of
RAS
is don’t care in read cycle.) When
WE
is
high at the falling edge of
RAS,
a normal write cycle is executed. After that,
WE
switches read/write cycles
as in a standard DRAM. In a transfer cycle, the direction of transfer is determined by
WE
level at the falling
edge of
RAS.
When
WE
is low, data is transferred from SAM to RAM (data is written into RAM), and when
WE
is high, data is transferred from RAM to SAM (data is read from RAM).
I/O0 – I/O3 (input/output pins):
I/O pins function as mask data at the falling edge of
RAS
(in mask write
mode). Data is written only to high I/O pins. Data on low I/O pins are masked and internal data are retained.
After that, they function as input/output pins as those of a standard DRAM.
DT/OE
(input pin):
DT/OE
pin functions as
DT
(data transfer) pin at the falling edge of
RAS
and as
O E
(output enable) pin after that. When
DT
is low at the falling edge of
RAS,
this cycle becomes a transfer
cycle. When
DT
is high at the falling edge of
RAS,
RAM and SAM operate independently.
SC (input pin):
SC is a basic SAM clock. In a serial read cycle, data outputs from an SI/O pin
synchronously with the rising edge of SC. In a serial write cycle, data on an SI/O pin at the rising edge of SC
is fetched into the SAM data register.
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