HXSR01608
HXSR01608
2M x 8 STATIC RAM
The monolithic, radiation hardened 16M bit Static
Random Access Memory (SRAM) in a 2M x 8
configuration is a high performance 2,097,152 word x 8
bit SRAM fabricated with Honeywell’s 150nm silicon-
on-insulator CMOS (S150) technology. It is designed
for use in low voltage systems operating in radiation
sensitive environments. The RAM operates over the full
military temperature range and requires a core supply
voltage of 1.8V +/- 0.15V and an I/O supply voltage of
3.3V ± 0.3V or 2.5V ± 0.2V.
proprietary design, layout and process hardening
techniques. There is no internal EDAC implemented.
It is a low power process with a minimum drawn feature
size of 150 nm. Less than 1
50mW typical power at
40MHz operation.
The SRAM is fully asynchronous
with a typical access time of 13 ns at 3.3V. A seven
transistor (7T) memory cell is used for superior single
event upset hardening, while four layer metal power
busing and the low collection volume SOI substrate
provide improved dose rate hardening.
Honeywell’s
state-of-the-art
S150
technology
is
radiation hardened through the use of advanced and
FEATURES
•
Fabricated on S150 Silicon On
Insulator (SOI) CMOS
•
150 nm Process (L
eff
= 110 nm)
•
Read Cycle Times
Typical =13 ns
Worst case = 20 ns
•
Write Cycle Times
Typical = 9 ns
Worst case = 12 ns
•
Asynchronous Operation
•
Total Dose =1X10
6
rad(Si)
•
Soft Error Rate
Heavy Ion =1x10
-12
Upsets/bit-day
Proton = 2x10
-12
Upsets/bit-day
•
Neutron =1x10
14
cm
-2
•
Dose Rate Upset
=1x10
10
rad(Si)/s
•
Dose Rate Survivability
=1x10
12
rad(Si)/s
•
No Latchup
•
Core Power Supply
1.8 V ± 0.15 V
•
I/O Power Supply
3.3 V ± 0.3 V
2.5 V ± 0.2 V
•
CMOS Compatible I/O
•
Operating Range is
-55°C to +125°C
•
40-Lead Flat Pack Package
HXSR01608
FUNCTIONAL DIAGRAM
Row
Driver
2,097,152 x 8
Memory Array
40 LEAD FLAT PACK PINOUT
VSS
A0
A1
A2
A3
A4
1
2
3
4
5
6
7
8
9
10
11
A(0-8)
HXSR01608
Top View
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VDD
A20
A19
A18
A17
A16
NOE
DQ7
DQ6
VSS
VDD2
DQ5
DQ4
A15
A14
A13
A12
A11
A10
VSS
A(9-20)
NWE
Column Decoder
Data Input/Output
NCS
DQ0
DQ1
VDD2
VSS
NOE
NCS
DQ2 12
DQ3 13
NWE 14
A5 15
A6 16
A7 17
A8 18
DQ(0-7)
A9 19
VDD 20
SIGNAL DEFINITIONS
A (0-20)
DQ (0-7)
NCS
Address input signals. Used to select a particular eight-bit word within the memory
array.
Bi-directional data signals. These function as data outputs during a read operation and
as data inputs during a write operation.
Negative Chip Select input signal. Setting to a low level allows normal read or write
operation. When at a high level, it sets the SRAM to a precharge condition and holds
the data output drivers in a high impedance state. If the NCS signal is not used it
must be connected to VSS.
By setting to a high level, the standby currents are reduced.
Negative Write Enable input signal. Setting to a low level activates a write operation
and holds the data output drivers in a high impedance state. When at a high level it
allows normal read operation.
Negative Output Enable input signal. Setting to a high level holds the data output
drivers in a high impedance state. When at a low level, the data output driver state is
defined by NCS and NWE. If this signal is not used, it must be connected to VSS.
Core operating voltage. Typical value of 1.8V
I/O Operating Voltage. Typical value of 3.3V or 2.5V
NWE
NOE
VDD
VDD2
TRUTH TABLE
NCS
L
L
H
NWE
H
L
X
NOE
L
X
X
Mode
Read
Write
Deselected
DQ
Data Out
Data In
High Z
X: VIH or VIL,
NOE=H: High Z output state maintained for NCS=X,
NWE=X
2
www.honeywell.com/radhard
HXSR01608
RADIATION CHARACTERISTICS
Total Ionizing Radiation Dose
The SRAM will meet all stated functional and electrical
specifications over the entire operating temperature
range after the specified total ionizing radiation dose. All
electrical and timing performance parameters will remain
within specifications, post rebound (based on
extrapolation),after an operational period of 10 years.
Total dose hardness is assured by wafer level testing of
process monitor transistors and RAM product using 10
KeV X
-ray. Transistor gate threshold shift correlations
have been made between 10 KeV X
-rays applied at a
6
dose rate of 1x10 rad(SiO
2
)/min at T= 25°C and gamma
rays (Cobalt 60 source) to ensure that wafer level X
-ray
testing is consistent with standard military radiation test
environments.
Transient Pulse Ionizing Radiation
The SRAM is capable of writing, reading, and retaining
stored data during and after exposure to a transient
ionizing radiation pulse, up to the specified transient
dose rate upset specification, when applied under
recommended operating conditions. It is recommended
to provide external power supply decoupling capacitors
to maintain VDD and VDD2 voltage levels during
transient events. The SRAM will meet any functional or
electrical specification after exposure to a radiation
pulse up to the transient dose rate survivability
specification, when applied under recommended
operating conditions. Note that the current conducted
during the pulse by the RAM inputs, outputs, and power
supply may significantly exceed the normal operating
levels. The application design must accommodate these
effects.
Neutron Radiation
The SRAM will meet any functional or timing
specification after exposure to the specified neutron
fluence under recommended operating or storage
conditions. This assumes equivalent neutron energy of 1
MeV.
Soft Error Rate
The SRAM is capable of meeting the specified Soft Error
Rate (SER), under recommended operating conditions.
The specification applies to both heavy ion and proton.
This hardness level is defined by the Adams 90% worst
case cosmic ray environment for geosynchronous orbits.
Latchup
The SRAM will not latch up due to any of the above
radiation exposure conditions when applied under
recommended operating conditions. Fabrication with the
SOI substrate material provides oxide isolation between
adjacent PMOS and NMOS transistors and eliminates
any potential SCR latchup structures. Sufficient
transistor body tie connections to the p- and n-channel
substrates are made to ensure no source/drain
snapback
occurs.
RADIATION-HARDNESS RATINGS (1)
Parameter
Total Dose
Transient Dose Rate Upset
Transient Dose Rate Survivability
Soft Error Rate
Neutron Fluence
(1)
Limits
=1X10
6
=1X10
10
=1X10
12
<1X10
-12
<2X10
-12
=1X10
14
Units
rad(Si)
rad(Si)/s
rad(Si)/s
Upsets/bit-day
N/cm
2
Test Conditions
T
A
=25°C, VDD2=3.6V, VDD=1.95V
Pulse width = 50 ns,X-ray, VDD2 = 3.0V,
VDD=1.65V, T
C
=25°C
Pulse width = 50 ns,X-ray, VDD2 = 3.6V,
VDD=1.95V, T
A
=25°C
VDD2=3.0V, VDD=1.65V, T
C
= 25 and 125°C,
Adams 90% worst case environment
1MeV equivalent energy, Unbiased, T
A
=25°C
Heavy Ion
Proton
Device will not latch up due to any of the specified radiation exposure conditions.
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3
HXSR01608
ABSOLUTE MAXIMUM RATINGS (1)
Symbol
VDD
VDD2
VPIN
TSTORE
TSOLDER
PD
IOUT
VPROT
TJ
PJC
Parameter
Min
Supply Voltage (core) (2)
Supply Voltage (I/O) (2)
Voltage on Any Pin (2)
Storage Temperature
Soldering Temperature (5)
Maximum Power Dissipation (3)
Average Output Current
Electrostatic Discharge Protection Voltage (4)
Maximum Junction Temperature
Package Thermal Resistance
40 Pin FP
(Junction-to-Case)
-0.5
-0.5
-0.5
-65
Rating
Max
2.4
4.4
VDD2+0.5
150
270
2.5
15
175
2.0
Units
Volts
Volts
Volts
°C
°C
W
mA
V
°C
°C/W
2000
(1) Stresses in excess of those listed above may result in immediate permanent damage to the device. These are stress ratings only,
and operation at these levels is not implied. Frequent or extended exposure to absolute maximum conditions may affect device
reliability.
(2) Voltage referenced to VSS.
(3) RAM power dissipation including output driver power dissipation due to external loading must not exceed this specification.
(4) Class 2 electrostatic discharge (ESD) input protection voltage per MIL-STD-883, Method 3015
(5) Maximum soldering temp of 270°C can be maintained for no more than 5 seconds.
RECOMMENDED OPERATING CONDITIONS (1)
Symbol
VDD
VDD2
TC
VPIN
VDD2/VDD Ramp Time
VDDD/ VDD PDT (2)
Parameter
Min
Supply Voltage (core)
Supply Voltage (I/O)
External Package
Temperature
Voltage on Any Pin
Supply Voltages Ramp Time
Power Supply Power Down
Time
1.65
3.0
2.3
-55
-0.3
5
Description
Typ
Max
1.80
3.3
2.5
25
1.95
3.6
2.7
125
VDD2+0.3
1.0
Units
Volts
Volts
°C
Volts
Second
msec
(1) Voltages referenced to Vss.
(2) Power Supplies must be turned off for power down time before turned back on.
CAPACITANCE (1)
Symbol
CA
CC
CD
Parameter
Address Input Capacitance
NCS, NOE, NWE Input
Capacitance
Data I/O, Capacitance
Worst Case (1)
Min
Max
5
15
7
Units
pF
pF
pF
Test Conditions
VIN=VDD or VSS, f=1 MHz
VIN=VDD or VSS, f=1 MHz
VIN=VDD or VSS, f=1 MHz
(1) This parameter is tested during initial qualification only.
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4
HXSR01608
DC ELECTRICAL CHARACTERISTICS (1)
Symbol
IDDSB
(4)
Parameter
Static Supply Current
TA=25°C
TA=85°C
TA=125°C
Dynamic Supply Current –
Deselected
Operating Current -
Disabled
Dynamic Supply Current,
Selected (Write)
1 MHz
2 MHz
10 MHz
25 MHz
40 MHz
Dynamic Supply Current,
Selected (Read)
1 MHz
2 MHz
10 MHz
25 MHz
40 MHz
Data Retention Current
TA=25°C
TA=125°C
Min
IDD
4
9
30
0.1
2
Max
IDD2
0.3
0.3
0.3
0.2
5
Units
Test Conditions
IDDOP1
IDDOP3
IDDOPW
mA
mA
mA
mA
mA
VDD=max, Iout=0mA, Inputs Stable
VDD=max, Iout=0mA, F=1MHz,
NCS=VIH (3)
VDD=max, Iout=0mA, F=40MHz,
NCS=VIH (3)
2
4
20
50
80
0.2
0.4
2
5
8
mA
mA
mA
mA
mA
VDD2 and VDD=max, NCS=VIL (1)
(2) (3)
IDDOPR
1
2
10
25
40
1
20
0.2
0.4
2
5
8
0.2
0.2
mA
mA
mA
mA
mA
mA
mA
VDD2 and VDD=max NCS=VIL (1)
(3)
IDR
VDD=1V, VDD2=2V
Symbol
II
IOZ
VIL
VIH
VOL
VOH
(1)
(2)
(3)
(4)
Parameter
Input Leakage Current
Output Leakage Current
Low-Level Input Voltage
High-Level Input Voltage
Low-Level Output Voltage
High-Level Output Voltage
Min
-5
-10
0.7xVDD2
Max
5
10
0.3xVDD2
0.4
Units
µA
µA
V
V
V
V
Test Conditions
Output = high Z
VDD2=3.0V or 2.5V
VDD2=3.6V or 2.4V
VDD2=3.0V, IOL = 10mA
VDD2=3.0V, IOH = 5mA
2.7
Worst case operating conditions: VDD2=2.3V to 3.6V, VDD=1.65V to 1.95V, -55°C to +125°C, post total dose at 25°C.
All inputs switching. DC average current.
All dynamic operating mode current measurements (IDDOPx) exclude standby mode current (IDDSB)
See graph below for typical static current values.
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5
PCB Design
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