KMMR16R84(6/8/C/G)C1
KMMR18R84(6/8/C/G)C1
Overview
Preliminary
4/6/8/12/16d RIMM
TM
Module with 128Mb RDRAMs
4/6/8/12/16d RIMM
TM
Module with 144Mb RDRAMs
Key Timing Parameters/Part Numbers
The following table lists the frequency and latency bins
available from RIMM modules. An optional ‘ S’ designator
instead of ‘R’ followed by ‘ hyphen(-)’ indicates low power
modules.
TABLE 1. Part Number by Freq. & Latency
Speed
Organization
I/O
Binning Freq.
MHz
-RG6
-RK8
-RM8
48M x 16/18
-RG6
-RK8
-RM8
64M x 16/18
-RG6
-RK8
-RM8
600
800
800
600
800
800
600
800
800
600
800
800
600
800
800
The Rambus
®
RIMM™ module is a general purpose high-
performance memory subsystem suitable for use in a broad
range of applications including computer memory, personal
computers, workstations, and other applications where high
bandwidth and low latency are required.
The Rambus RIMM module consists of 128Mb/144Mb
Direct Rambus DRAM devices. These are extremely high-
speed CMOS DRAMs organized as 8M words by 16 or 18
bits. The use of Rambus Signaling Level (RSL) technology
permits 600MHz or 800MHz transfer rates while using
conventional system and board design technologies.
RDRAM devices are capable of sustained data transfers at
1.25 ns per two bytes (10ns per 16 bytes).
The RDRAM architecture enables the highest sustained
bandwidth for multiple, simultaneous, randomly addressed,
memory transactions. The separate control and data buses
with independent row and column control yield over 95%
bus efficiency. The RDRAM's 32-banks architecture
supports up to four simultaneous transactions per device.
t
rac
(Row
Access
Time) ns
53
45
40
53
45
40
53
45
40
53
45
40
53
45
40
Part Number
a
32M x 16/18
KMMR16/18R84C1-RG6
KMMR16/18R84C1-RK8
KMMR16/18R84C1-RM8
KMMR16/18R86C1-RG6
KMMR16/18R86C1-RK8
KMMR16/18R86C1-RM8
KMMR16/18R88C1-RG6
KMMR16/18R88C1-RK8
KMMR16/18R88C1-RM8
KMMR16/18R8CC1-RG6
KMMR16/18R8CC1-RK8
KMMR16/18R8CC1-RM8
KMMR16/18R8GC1-RG6
KMMR16/18R8GC1-RK8
KMMR16/18R8GC1-RM8
Features
♦
High speed 800 and 600MHz RDRAM storage
♦
184 edge connector pads with 1mm pad spacing
♦
Maximum module PCB size : 133.5mm x 31.75mm x
96M x 16/18
-RG6
-RK8
-RM8
128M x 16/18
-RG6
-RK8
-RM8
1.37mm (5.21” x 1.25” x 0.05”)
♦
Each RDRAM has 32 banks, for a total of 512, 384, 256,
192, or 128 banks on each 256/288MB, 192/216MB,
128/144MB, 96/108MB, or 64/72MB module respectively
♦
Gold plated edge connector pad contacts
♦
Serial Presence Detect(SPD) support
♦
Operates from a 2.5 volt supply (±5%)
♦
Low power and powerdown self refresh modes
♦
Separate Row and Column buses for higher efficiency
♦
RDRAMs use
µ−
BGA package type
a. -S designator is used for modules with lower self-refresh current.
Form Factor
The Rambus RIMM modules are offered in a 184-pad 1mm
edge connector pad pitch form factor suitable for 184 contact
RIMM connectors. The RIMM module is suitable for
desktop and other system applications.
Note: On two sided modules, RDRAMs are also installed on bottem side of PCB.
Figure 1: Rambus RIMM Module without heat spreader
Page 1
Rev.0.9 Apr. 1999
KMMR16R84(6/8/C/G)C1
KMMR18R84(6/8/C/G)C1
Preliminary
4/6/8/12/16d RIMM
TM
Module with 128Mb RDRAMs
4/6/8/12/16d RIMM
TM
Module with 144Mb RDRAMs
TABLE 2. Module Pad Number and Signal Names
Pin
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
Pin Name
Gnd
LDQA8
Gnd
LDQA6
Gnd
LDQA4
Gnd
LDQA2
Gnd
LDQA0
Gnd
LCTMN
Gnd
LCTM
Gnd
NC
Gnd
LROW1
Gnd
LCOL4
Gnd
LCOL2
Gnd
LCOL0
Gnd
LDQB1
Gnd
LDQB3
Gnd
LDQB5
Gnd
LDQB7
Gnd
LSCK
Vcmos
SOUT
Vcmos
NC
Gnd
NC
Vdd
Vdd
NC
NC
NC
NC
Pin
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
Pin Name
Gnd
LDQA7
Gnd
LDQA5
Gnd
LDQA3
Gnd
LDQA1
Gnd
LCFM
Gnd
LCFMN
Gnd
NC
Gnd
LROW2
Gnd
LROW0
Gnd
LCOL3
Gnd
LCOL1
Gnd
LDQB0
Gnd
LDQB2
Gnd
LDQB4
Gnd
LDQB6
Gnd
LDQB8
Gnd
LCMD
Vcmos
SIN
Vcmos
NC
Gnd
NC
Vdd
Vdd
NC
NC
NC
NC
Pin
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82
A83
A84
A85
A86
A87
A88
A89
A90
A91
A92
Pin Name
NC
NC
NC
NC
Vref
Gnd
SCL
Vdd
SDA
SVdd
SWP
Vdd
RSCK
Gnd
RDQB7
Gnd
RDQB5
Gnd
RDQB3
Gnd
RDQB1
Gnd
RCOL0
Gnd
RCOL2
Gnd
RCOL4
Gnd
RROW1
Gnd
NC
Gnd
RCTM
Gnd
RCTMN
Gnd
RDQA0
Gnd
RDQA2
Gnd
RDQA4
Gnd
RDQA6
Gnd
RDQA8
Gnd
Pin
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82
B83
B84
B85
B86
B87
B88
B89
B90
B91
B92
Pin Name
NC
NC
NC
NC
Vref
Gnd
SA0
Vdd
SA1
SVdd
SA2
Vdd
RCMD
Gnd
RDQB8
Gnd
RDQB6
Gnd
RDQB4
Gnd
RDQB2
Gnd
RDQB0
Gnd
RCOL1
Gnd
RCOL3
Gnd
RROW0
Gnd
RROW2
Gnd
NC
Gnd
RCFMN
Gnd
RCFM
Gnd
RDQA1
Gnd
RDQA3
Gnd
RDQA5
Gnd
RDQA7
Gnd
Page 2
Rev.0.9 Apr. 1999
KMMR16R84(6/8/C/G)C1
KMMR18R84(6/8/C/G)C1
Preliminary
4/6/8/12/16d RIMM
TM
Module with 128Mb RDRAMs
4/6/8/12/16d RIMM
TM
Module with 144Mb RDRAMs
TABLE 3. Module Connector Pad Description
Signal
Gnd
Pins
A1, A3, A5, A7, A9, A11, A13, A15,
A17, A19, A21, A23, A25, A27, A29,
A31, A33, A39, A52, A60, A62, A64,
A66, A68, A70, A72, A74, A76, A78,
A80, A82, A84, A86, A88, A90, A92,
B1, B3, B5, B7, B9, B11, B13, B15,
B17, B19, B21, B23, B25, B27, B29,
B31, B33, B39, B52, B60, B62, B64,
B66, B68, B70, B72, B74, B76, B78,
B80, B82, B84, B86, B88, B90, B92
B10
B12
B34
A20, B20, A22, B22, A24
A14
A12
A2, B2, A4, B4, A6, B6, A8, B8, A10
I/O
B32, A32, B30, A30, B28, A28, B26,
A26, B24
B16, A18, B18
A34
A16, B14, A38, B38, A40, B40, A43,
B43, A44, B44, A45, B45, A46, B46,
A47, B47, A48, B48, A49, B49, A50,
B50, A77, B79
B83
B81
B59
I
RCOL4..
RCOL0
A73, B73, A71, B71, A69
V
CMOS
I
I
RSL
RSL
RSL
I
I
I
I
I
I
RSL
RSL
V
CMOS
RSL
RSL
RSL
I/O
Type
Description
Ground reference for RDRAM core and interface. 72
PCB connector pads.
LCFM
LCFMN
LCMD
LCOL4..
LCOL0
LCTM
LCTMN
LDQA8..
LDQA0
LDQB8..
LDQB0
LROW2..
LROW0
LSCK
NC
Clock from master. Interface clock used for receiving
RSL signals from the Channel. Positive polarity.
Clock from master. Interface clock used for receiving
RSL signals from the Channel. Negative polarity.
Serial Command used to read from and write to the con-
trol registers. Also used for power management.
Column bus. 5-bit bus containing control and address
information for column accesses.
Clock to master. Interface clock used for transmitting
RSL signals to the Channel. Positive polarity.
Clock to master. Interface clock used for transmitting
RSL signals to the Channel. Negative polarity.
Data bus A. A 9-bit bus carrying a byte of read or write
data between the Channel and the RDRAM. LDQA8 is
non-functional on modules with x16 RDRAM devices
Data bus B. A 9-bit bus carrying a byte of read or write
data between the Channel and the RDRAM. LDQB8 is
non-functional on modules with x16 RDRAM devices.
Row bus. 3-bit bus containing control and address infor-
mation for row accesses.
Serial Clock input. Clock source used to read from and
write to the RDRAM control registers.
These pads are not connected. These 24 connector pads
are reserved for future use.
I/O
RSL
I
I
RSL
V
CMOS
RCFM
RCFMN
RCMD
Clock from master. Interface clock used for receiving
RSL signals from the Channel. Positive polarity.
Clock from master. Interface clock used for receiving
RSL signals from the Channel. Negative polarity.
Serial Command Input. Pin used to read from and write
to the control registers. Also used for power manage-
ment.
Column bus. 5-bit bus containing control and address
information for column accesses.
I
RSL
Page 3
Rev.0.9 Apr. 1999
KMMR16R84(6/8/C/G)C1
KMMR18R84(6/8/C/G)C1
Signal
RCTM
RCTMN
RDQA8..
RDQA0
RDQB8..
RDQB0
RROW2..
RROW0
RSCK
SA0
SA1
SA2
SCL
SDA
SIN
Pins
A79
A81
Preliminary
4/6/8/12/16d RIMM
TM
Module with 128Mb RDRAMs
4/6/8/12/16d RIMM
TM
Module with 144Mb RDRAMs
I/O
I
I
Type
RSL
RSL
Description
Clock to master. Interface clock used for transmitting
RSL signals to the Channel. Positive polarity.
Clock to master. Interface clock used for transmitting
RSL signals to the Channel. Negative polarity.
Data bus A. A 9-bit bus carrying a byte of read or write
data between the Channel and the RDRAM. RDQA8 is
non-functional on modules x16 RDRAM devices.
Data bus B. A 9-bit bus carrying a byte of read or write
data between the Channel and the RDRAM. RDQB8 is
non-functional on modules x16 RDRAM devices.
Row bus. 3-bit bus containing control and address infor-
mation for row accesses.
Serial Clock input. Clock source used to read from and
write to the RDRAM control registers.
Serial Presence Detect Address 0.
Serial Presence Detect Address 1.
Serial Presence Detect Address 2.
Serial Presence Detect Clock.
Serial Presence Detect Data (Open Collector I/O).
Serial I/O for reading from and writing to the control
registers. Attaches to SIO0 of the first RDRAM on the
module.
Serial I/O for reading from and writing to the control
registers. Attaches to SIO1 of the last RDRAM on the
module.
SPD Voltage. Used for signals SCL, SDA, SWE, SA0,
SA1 and SA2.
I
SV
DD
Serial Presence Detect Write Protect (active high). When
low, the SPD can be written as well as read.
CMOS I/O Voltage. Used for signals CMD, SCK, SIN,
SOUT.
Supply voltage for the RDRAM core and interface logic.
Logic threshold reference voltage for RSL signals.
A91, B91, A89, B89, A87, B87, A85,
B85, A83
B61, A61, B63, A63, B65, A65, B67,
A67, B69
B77, A75, B75
A59
B53
B55
B57
A53
A55
B36
I/O
RSL
I/O
RSL
I
I
I
I
I
I
I/O
I/O
RSL
V
CMOS
SV
DD
SV
DD
SV
DD
SV
DD
SV
DD
V
CMOS
SOUT
A36
I/O
V
CMOS
SV
DD
SWP
V
CMOS
Vdd
Vref
A56, B56
A57
A35, B35, A37, B37
A41, A42, A54, A58, B41, B42, B54,
B58
A51, B51
Page 4
Rev.0.9 Apr. 1999
KMMR16R84(6/8/C/G)C1
KMMR18R84(6/8/C/G)C1
Preliminary
4/6/8/12/16d RIMM
TM
Module with 128Mb RDRAMs
4/6/8/12/16d RIMM
TM
Module with 144Mb RDRAMs
LDQA8
LDQA7
LDQA6
LDQA5
LDQA4
LDQA3
LDQA2
LDQA1
LDQA0
LCFM
LCFMN
LCTM
LCTMN
LROW2
LROW1
LROW0
LCOL4
LCOL3
LCOL2
LCOL1
LCOL0
LDQB0
LDQB1
LDQB2
LDQB3
LDQB4
LDQB5
LDQB6
LDQB7
LDQB8
LCMD
RCMD
LSCK
Note 1. Rambus Channel signals form a loop through
the RIMM module, with the exception of the SIO chain.
Note 2. See Serial Presence Detection Specification for
information on the SPD device and its contents.
V
REF
•
•
•
SIN
SIO0
SIO1
SCK
CMD
Vref
SIO0
SIO1
SCK
CMD
Vref
SIO0
SIO1
SCK
CMD
Vref
SIO0
SIO1
SCK
CMD
Vref
SOUT
Vdd
DQA8
DQA7
DQA6
DQA5
DQA4
DQA3
DQA2
DQA1
DQA0
CFM
CFMN
CTM
CTMN
ROW2
ROW1
ROW0
COL4
COL3
COL2
COL1
COL0
DQB0
DQB1
DQB2
DQB3
DQB4
DQB5
DQB6
DQB7
DQB8
U1
Direct RDRAM (128/144Mb)
DQA8
DQA7
DQA6
DQA5
DQA4
DQA3
DQA2
DQA1
DQA0
CFM
CFMN
CTM
CTMN
ROW2
ROW1
ROW0
COL4
COL3
COL2
COL1
COL0
DQB0
DQB1
DQB2
DQB3
DQB4
DQB5
DQB6
DQB7
DQB8
Gnd
V
REF
2 per
RDRAM
0.1µF
U2
Direct RDRAM (128/144Mb)
DQA8
DQA7
DQA6
DQA5
DQA4
DQA3
DQA2
DQA1
DQA0
CFM
CFMN
CTM
CTMN
ROW2
ROW1
ROW0
COL4
COL3
COL2
COL1
COL0
DQB0
DQB1
DQB2
DQB3
DQB4
DQB5
DQB6
DQB7
DQB8
Gnd
V
CMOS
1 per
2 RDRAMs
Plus one
Near Connector
0.1µF
U3
Direct RDRAM (128/144Mb)
•
•
•
DQA8
DQA7
DQA6
DQA5
DQA4
DQA3
DQA2
DQA1
DQA0
CFM
CFMN
CTM
CTMN
ROW2
ROW1
ROW0
COL4
COL3
COL2
COL1
COL0
DQB0
DQB1
DQB2
DQB3
DQB4
DQB5
DQB6
DQB7
DQB8
Gnd
1 per
2 RDRAMs
0.1
µF
Module
Capacity
256MB
192MB
128MB
96MB
64MB
N
16
12
8
6
4
UN
Direct RDRAM (128/144Mb)
RSCK
RDQA8
RDQA7
RDQA6
RDQA5
RDQA4
RDQA3
RDQA2
RDQA1
RDQA0
RCFM
RCFMN
RCTM
RCTMN
RROW2
RROW1
RROW0
RCOL4
RCOL3
RCOL2
RCOL1
RCOL0
RDQB0
RDQB1
RDQB2
RDQB3
RDQB4
RDQB5
RDQB6
RDQB7
RDQB8
SV
DD
Vcc
SCL
SWP
47KΩ
SA0
SA1
SA2
SCL
SDA
WP
A0 A1 A2
SDA
Serial Presence Detect
SV
DD
U0
Gnd
0.1
µF
Figure 2: RIMM Module Functional Diagram
Page 5
Rev.0.9 Apr. 1999
京公网安备 11010802033920号
EEWORLD
