KADxx0300B - Txxx
Document Title
Multi-Chip Package MEMORY
MCP MEMORY
128M Bit (Two Dual Bank 64M Bit) NOR Flash Memory / 32M Bit (2Mx16) UtRAM
Revision History
Revision No. History
0.0
0.1
Initial Draft
Draft Date
August 9, 2002
Remark
Preliminary
Revised (UtRAM)
November 29, 2002 Preliminary
- Changed I
CC
1u(Typ.) from 4mA to 6mA
- Changed I
CC
1u(Max.) from 7mA to 10mA
- Changed Cycle time of I
CC
2 from ’Min’ to ’tRC+3tPC’ in DC Characteristics
- Added Page Cycle(tPC) and Page Access Time(tPA) in AC Characteristics
- Added TIMING WAVEFORM OF PAGE CYCLE(READ ONLY) in Timing
Diagrams
Finalized
Revised (UtRAM)
- Changed t
OH (MIN)
From 10ns to 5ns in AC Characteristics
- Changed Power up Sequence
- Deleted Technical Note
Revised(NOR)
- Release the stand-by current from typ. 10uA(max. 36uA) to typ.
20uA(max. 60uA).
May 23, 2003
Final
1.0
1.1
June 18, 2003
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
-1-
Revision 1.1
June 2003
KADxx0300B - Txxx
Multi-Chip Package MEMORY
MCP MEMORY
128M Bit (Two Dual Bank 64M Bit) NOR Flash Memory / 32M Bit (2Mx16) UtRAM
FEATURES
•
Power Supply Voltage : 2.7V to 3.1V
•
Organization
- Flash :Two 64Mb : Each of K8D6316UT(B)M, Byte/Word Mode
- UtRAM : 2,097,152 x 16 bit
•
Two Chip Enable (Flash)
- Two CE balls control each internal Flash Memory
•
Access Time (@2.7V)
- Flash : 70 ns, UtRAM : 70 ns
•
Power Consumption
- Flash (typical value)
Read Current : 14 mA (@5MHz)
Program/Erase Current : 15 mA
Standby mode/Autosleep mode :
20
µA
Read while Program or Read while Erase : 25 mA
- UtRAM (typical value)
Operating Current : 30 mA
Standby Current : 60
µA
•
Secode(Security Code) Block : Extra 64KB Block (Flash)
•
Support Common Flash Memory Interface
•
Block Group Protection / Unprotection (Flash)
•
Flash Bank Size : 16Mb / 48Mb , 32Mb / 32Mb
•
Flash Endurance : 100,000 Program/Erase Cycles Minimum
•
Operating Temperature : -40°C ~ 85°C
•
Package : 69-ball TBGA Type - 8 x 11.6mm, 0.8 mm pitch
1.4mm(max.) Thickness
GENERAL DESCRIPTION
The KADxx0300B featuring single 3.0V power supply is a Multi
Chip Package Memory which combines two 64Mbit Dual Bank
Flash and 32Mbit UtRAM.
The each of 64Mbit Flash memory is organized as 8M x8 or 4M
x16 bit and 32Mbit UtRAM is organized as 2M x16 bit. The mem-
ory architecture of each flash memory is designed to divide its
memory arrays into 135 blocks and this provides highly flexible
erase and program capability. Each Flash memory is capable of
reading data from one bank while programming or erasing in the
other bank with dual bank organization.
The Flash memory performs a program operation in units of 8 bits
(Byte) or 16 bits (Word) and erases in units of a block. Single or
multiple blocks can be erased. The block erase operation is com-
pleted for typically 0.7sec.
The UtRAM is fabricated by SAMSUNG′s advanced CMOS tech-
nology using one transistor memory cell. The device supports
deep power down mode for low standby current.
The KADxx0300B is suitable for the memory of mobile communi-
cation system to reduce mount area. This device is available in
69-ball TBGA Type package.
BALL DESCRIPTION
Ball Name
Description
Address Input Balls (Common)
Address Input Balls (Flash Memory)
Data Input/Output Balls (Common)
Hardware Reset (Flash Memory)
Write Protection / Acceleration Program
(Flash Memory)
Upper Byte Enable
(UtRAM)
Lower Byte Enable
(UtRAM)
Word/Byte selection (Flash Memory)
Flash Chip Enable 1 (Flash Memory)
Flash Chip Enable 2 (Flash Memory)
Chip Enable
(UtRAM)
Deep Power Down (UtRAM)
BALL CONFIGURATION
1
A
B
C
D
E
F
G
H
J
K
D.N.U
D.N.U
D.N.U
A
0
to A
20
2
3
4
5
6
7
8
9
10
D.N.U
A-1, A
21
DQ
0
to DQ
15
D.N.U D.N.U
WP/
ACC
RESET
WP/ACC
D.N.U
A3
A7
LB
UB
A18
A17
WE
A8
A19
A11
A12
A15
A6
RESET
ZZ
A20
UB
LB
A2
A1
A5
RY/BY
A9
A10
A13
A21
BYTE
F
CE
F
1
CE
F
2
CS
U
ZZ
WE
A4
A14
CE
F
2 D.N.U
D.N.U
A0
V
SS
DQ1
DQ6
N.C
A16
D.N.U
CE
F
1
CS
U
OE
DQ0
DQ9
DQ10
DQ3
Vcc
F
DQ4
DQ13
DQ15
BYTE
F
/A-1
DQ7
Vss
Write Enable (Common)
Output Enable (Common)
Ready/Busy (Flash memory)
Power Supply
(UtRAM)
Power Supply (Flash Memory)
Ground (Common)
Do Not Use
No Connection
Vcc
U
DQ12
OE
RY/BY
Vcc
U
D.N.U
DQ8
DQ2
DQ11
N.C
DQ5
DQ14
D.N.U D.N.U
Vcc
F
Vss
D.N.U
N.C
69 Ball TBGA , 0.8mm Pitch
Top View (Ball Down)
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to change products and specifications without notice.
-2-
Revision 1.1
June 2003
KADxx0300B - Txxx
ORDERING INFORMATION
MCP MEMORY
K A D xx 0 3 0 0 B - T
Samsung
MCP Memory(3chip)
Device Type
D: NOR + NOR + UtRAM
NOR Flash Density
Two 64Mb NOR : Vcc : 3.0V, Org.:x8/x16
Refer to the below table
LLL
Access Time
LLL: NOR(70ns) UtRAM(70ns)
NNL: NOR(80ns) UtRAM(70ns)
Package
T = 69 TBGA (8x11.6)
Version
B = 3rd Generation
DRAM I/F, Density (Vcc, Org.)
None
SRAM Density (Vcc, Org.)
None
NAND Flash Density (Vcc, Org.)
None
UtRAM Density (Vcc, Org.)
3: 32M(2M x16), 3.0V, x16
64Mb - NOR 1
Controlled by CE
F
1
Bank Size
05
06
07
08
09
10
16Mb/48Mb
16Mb/48Mb
16Mb/48Mb
32Mb/32Mb
32Mb/32Mb
32Mb/32Mb
Boot Block Type
Top Boot Block
Top Boot Block
Bottom Boot Block
Top Boot Block
Top Boot Block
Bottom Boot Block
64Mb - NOR 2
Controlled by CE
F
2
Bank Size
16Mb/48Mb
16Mb/48Mb
16Mb/48Mb
32Mb/32Mb
32Mb/32Mb
32Mb/32Mb
Boot Block Type
Bottom Boot Block
Top Boot Block
Bottom Boot Block
Bottom Boot Block
Top Boot Block
Bottom Boot Block
-3-
Revision 1.1
June 2003
Power technology
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