PRELIMINARY
‡
64Mb: x16, x32
SYNCFLASH MEMORY
SYNCFLASH
®
MEMORY
Features
• PC133 SDRAM-compatible read timing
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access
• Programmable burst lengths:
1, 2, 4, 8, or full page (read)
1, 2, 4, or 8 (write)
• LVTTL-compatible inputs and outputs
• Single 3.0V–3.6V power supply
Additional V
HH
hardware protect mode (RP#)
• Supports CAS latency of 1, 2, and 3
• Four-bank architecture supports true concurrent
operation with zero latency
Read any bank while programming or erasing any
other bank
• Deep power-down mode: 300µA (MAX)
• Cross-compatible Flash memory command set.
MT28S4M16B1LC– 1 Meg x 16 x 4 banks
MT28S2M32B1LC– 512K x 32 x 4 banks
Pin Assignment (Top View)
86-Pin TSOP
x16
V
CC
DQ0
V
CC
Q
DQ1
DQ2
V
SS
Q
DQ3
DQ4
V
CC
Q
DQ5
DQ6
V
SS
Q
DQ7
NC
V
CC
DQM0
WE#
CAS#
RAS#
CS#
NC
BA0
BA1
A10
A0
A1
A2
MCL
V
CC
RP#
DNU
V
SS
Q
DNU
DNU
V
CC
Q
DNU
DNU
V
SS
Q
DNU
DNU
V
CC
Q
DNU
V
CC
x32
V
CC
DQ0
V
CC
Q
DQ1
DQ2
V
SS
Q
DQ3
DQ4
V
CC
Q
DQ5
DQ6
V
SS
Q
DQ7
NC
V
CC
DQM0
WE#
CAS#
RAS#
CS#
NC
BA0
BA1
A10
A0
A1
A2
DQM2
V
CC
RP#
DQ16
V
SS
Q
DQ17
DQ18
V
CC
Q
DQ19
DQ20
V
SS
Q
DQ21
DQ22
V
CC
Q
DQ23
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
x32
V
SS
DQ15
V
SS
Q
DQ14
DQ13
V
CC
Q
DQ12
DQ11
V
SS
Q
DQ10
DQ9
V
CC
Q
DQ8
NC
V
SS
DQM1
DNU
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
V
SS
V
CC
P
DQ31
V
CC
Q
DQ30
DQ29
V
SS
Q
DQ28
DQ27
V
CC
Q
DQ26
DQ25
V
SS
Q
DQ24
V
SS
x16
V
SS
DQ15
V
SS
Q
DQ14
DQ13
V
CC
Q
DQ12
DQ11
V
SS
Q
DQ10
DQ9
V
CC
Q
DQ8
NC
V
SS
DQM1
A9
NC
CLK
CKE
A11
A8
A7
A6
A5
A4
A3
MCL
V
SS
V
CC
P
DNU
V
CC
Q
DNU
DNU
V
SS
Q
DNU
DNU
V
CC
Q
DNU
DNU
V
SS
Q
DNU
V
SS
Options
• Configuration
4 Meg x 16 (1 Meg x 16 x 4 banks)
2 Meg x 32 (512K x 32 x 4 banks
• Read Timing (Cycle Time)
5.4ns @ CL3 (143 MHz)
5.4ns @ CL3 (133 MHz)
• Packages
86-pin OCPL
2
TSOP (400 mil)
90-ball FBGA
• Operating Temperature Range
Commercial (0ºC to +70ºC)
Extended (-40ºC to +85ºC)
NOTE:
1. Contact factory for availability.
2.Off-center parting line.
Marking
4M16
2M32
-7E
-75
TG
FG
None
ET
1
NOTE: 1.The # symbol indicates signal is active LOW.
2.FBGA ball assignment is on the next page.
Key Timing Parameters
ACCESS TIME
SPEED
GRADE
-7E
-7E
-75
-75
CLOCK
FREQUENCY
143 MHz
133 MHz
133 MHz
100 MHz
6
5.4ns
5.4ns
CL = 2*
CL = 3*
5.4ns
SETUP
TIME
1.5ns
1.5ns
1.5ns
1.5ns
HOLD
TIME
0.8ns
0.8ns
0.8ns
0.8ns
Part Number Example:
MT28S4M16B1LCTG-7E
* CL = CAS (READ) Latency
64Mb: x16, x 32 SyncFlash Memory
MT28S4M16B1LC_3.fm - Rev. 11/02
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
‡
PRODUCTS
AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.
PRELIMINARY
64Mb: x16, x32
SYNCFLASH MEMORY
FBGA Ball Assignment (Top View)
90-Ball FBGA – 4 Meg x 16
90-Ball FBGA – 2 Meg x 32
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
DNU
2
DNU
3
V
SS
7
Vcc
8
DNU
9
DNU
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
DQ26
2
DQ24
3
V
SS
7
Vcc
8
DQ23
9
DQ21
DNU
VccQ
V
SS
Q
VccQ
V
SS
Q
DNU
DQ28
VccQ
V
SS
Q
VccQ
V
SS
Q
DQ19
V
SS
Q
DNU
DNU
DNU
DNU
VccQ
V
SS
Q
DQ27
DQ25
DQ22
DQ20
VccQ
V
SS
Q
DNU
DNU
DNU
DNU
VccQ
V
SS
Q
DQ29
DQ30
DQ17
DQ18
VccQ
VccQ
DNU
NC
NC
DNU
VssQ
VccQ
DQ31
NC
NC
DQ16
VssQ
V
SS
MCL
A3
A2
MCL
Vcc
V
SS
DQM3
A3
A2
DQM2
Vcc
A4
A5
A6
A10
A0
A1
A4
A5
A6
A10
A0
A1
A7
A8
VccP
NC
BA1
NC
A7
A8
VccP
NC
BA1
NC
CLK
CKE
A11
BA0
CS#
RAS#
CLK
CKE
A9
BA0
CS#
RAS#
DQM1
RP#
A9
CAS#
WE#
DQM0
DQM1
RP#
DNU
CAS#
WE#
DQM0
VccQ
DQ8
Vss
Vcc
DQ7
V
SS
Q
VccQ
DQ8
Vss
Vcc
DQ7
V
SS
Q
V
SS
Q
DQ10
DQ9
DQ6
DQ5
VccQ
V
SS
Q
DQ10
DQ9
DQ6
DQ5
VccQ
V
SS
Q
DQ12
DQ14
DQ1
DQ3
VccQ
V
SS
Q
DQ12
DQ14
DQ1
DQ3
VccQ
DQ11
VccQ
V
SS
Q
VccQ
V
SS
Q
DQ4
DQ11
VccQ
V
SS
Q
VccQ
V
SS
Q
DQ4
DQ13
DQ15
Vss
Vcc
DQ0
DQ2
DQ13
DQ15
Vss
Vcc
DQ0
DQ2
64Mb: x16, x 32 SyncFlash Memory
MT28S4M16B1LC_3.fm - Rev 11/02
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
PRELIMINARY
64Mb: x16, x32
SYNCFLASH MEMORY
General Description
This 64Mb SyncFlash
®
data sheet is divided into
two major sections. The SDRAM Interface Functional
Description details compatibility with the SDRAM
memory, and the Flash Memory Functional Descrip-
tion specifies the symmetrical-sectored Flash architec-
ture and functional commands.
Micron’s 64Mb SyncFlash devices are nonvolatile,
electrically sector-erasable (Flash), programmable
read-only memory containing 67,108,864 bits. Each of
the x16’s 16,777,216-bit banks is organized as 4,096
rows by 256 columns by 16 bits. Each of the x32’s
16,777,216-bit banks is organized as 2,048 rows by 256
columns by 32 bits.
The 64Mb devices are organized into 16 indepen-
dently erasable blocks. To ensure that critical firmware
is protected from accidental erasure or overwrite, the
devices feature sixteen (x32: 128K-Dword; x16: 256K-
word) hardware and software-lockable blocks.
A four-bank architecture supports true concurrent
operations. A read access to any bank can occur simul-
taneously with a background PROGRAM or ERASE
operation to any other bank.
SyncFlash memory has a synchronous interface (all
signals are registered on the positive edge of the clock
signal, CLK). Read accesses to the memory are burst
oriented; accesses start at a selected location and con-
tinue for a programmed number of locations in a pro-
grammed sequence. Accesses begin with the
registration of an ACTIVE command, followed by a
READ command. The address bits registered coinci-
dent with the ACTIVE command are used to select the
bank and row to be accessed. The address bits regis-
tered coincident with the READ command are used to
select the starting column location for the burst
access.
The 64Mb devices provide for programmable read
burst lengths of 1, 2, 4, or 8 locations, or the full page,
with a burst terminate option. The x16 device features
an 8-word internal write buffer and the x32 features an
8-Dword internal write buffer that support mode regis-
ter programmed burst write compatibility of 1, 2, 4, or
8 locations.
SyncFlash memory uses an internal pipelined archi-
tecture to achieve high-speed operation.
The 64Mb devices are designed to operate in 3.3V,
low-power memory systems. A deep power-down
mode is provided, along with a power-saving standby
mode. All inputs and outputs are LVTTL-compatible.
SyncFlash memory offers substantial advances in
Flash operating performance, including the ability to
synchronously burst data at a high data rate with auto-
matic column-address generation and the capability
to randomly change column addresses on each clock
cycle during a burst access.
All Flash operations are performed using either a
hardware command sequence (HCS) or a software
command sequence (SCS). The HCS operations are
used by memory controllers with native SyncFlash
support. Standard SDRAM controllers can use SCS
operation to perform Flash operations.
Please refer to Micron’s Web site (www.micron.com/
flash)
for the latest data sheet.
Device Marking
Due to the size of the package, Micron’s standard
part number is not printed on the top of each device.
Instead, an abbreviated device mark comprised of a
five-digit alphanumeric code is used. The abbreviated
device marks are cross referenced to Micron part num-
bers in Table 1.
Table 1:
Cross Reference for
Abbreviated Device Marks
PRODUCT
SAMPLE
MARKING MARKING
PART NUMBER
MT28S4M16B1LCFG-75
MT28S4M16B1LCFG-7E
MT28S4M32B1LCFG-75
MT28S4M32B1LCFG-7E
FW402
FW403
FW302
FW303
FQ402
FQ403
FQ302
FQ303
64Mb: x16, x 32 SyncFlash Memory
MT28S4M16B1LC_3.fm - Rev 11/02
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
PRELIMINARY
64Mb: x16, x32
SYNCFLASH MEMORY
Table of Contents
Features............................................................................1
Pin Assignment (Top View)
86-Pin TSOP............................................................1
Key Timing Parameters............................................1
FBGA BALL ASSIGNMENT (Top View)
90-Ball FBGA – 4 Meg x 16 ............................................2
90-Ball FBGA – 2 Meg x 32 ............................................2
General Description ........................................................3
Device Marking ...............................................................3
Table 1 Cross Reference for Abbreviated
Device Marks ..........................................................3
Table of Contents ............................................................4
Functional Block Diagram
4 Meg x 16 ...............................................................6
Functional Block Diagram
2 Meg x 32 ...............................................................7
Pin and Ball Descriptions ........................................8
SDRAM Interface...........................................................10
FUNCTIONAL DESCRIPTION .....................................10
Initialization ................................................................10
Register Definition ......................................................10
Mode Register ...........................................................10
Burst Length ..............................................................10
Figure 1, Mode Register Definition .......................11
Table 2 Burst Definition.........................................11
Burst Type .................................................................12
CAS Latency...............................................................12
Figure 2, CAS Latency.............................................12
Operating Mode........................................................12
Write Burst Mode......................................................12
Table 3 CAS Latency .............................................. 12
COMMANDS .................................................................13
Truth Table 1...........................................................13
SDRAM-Compatible Interface Commands
and DQM Operation ........................................... 13
COMMANDS .................................................................14
TRUTH TABLE 2a – HARDWARE COMMAND
SEQUENCES (HCS)..............................................14
Truth Table 2b – Software Command
Sequences (SCS) ...................................................15
COMMAND INHIBIT ....................................................18
NO Operation (NOP) ..................................................18
LOAD MODE REGISTER ............................................18
ACTIVE.........................................................................18
READ ............................................................................18
WRITE ..........................................................................18
ACTIVE TERMINATE ..................................................18
BURST TERMINATE ...................................................18
LOAD COMMAND REGISTER (HCS Only) ...............18
Operation ...................................................................... 19
BANK/ROW ACTIVATION ...................................... 19
Figure 3, Activating a Specific Row
in a Specific Bank ................................................ 19
Figure 4, Example: Meeting
t
RCD (MIN)
When 2 <
t
RCD (MIN)/
t
CK
≤
3............................ 19
READs ....................................................................... 20
Figure 5, READ Command.................................... 20
Figure 6, CAS Latency............................................ 20
Figure 7, Consecutive Read Bursts....................... 21
Figure 8, Random Read Accesses
Within a Page ....................................................... 22
Figure 9, HCS READ to WRITE ............................. 23
Figure 10, HCS READ to WRITE with Extra
Clock Cycle........................................................... 23
Figure 11, Terminating a Read Burst ................... 24
Write Bursts .................................................................. 25
ACTIVE TERMINATE ................................................. 25
Power-Down............................................................... 25
Figure 12, WRITE Command ................................ 25
Figure 13, Write Burst............................................ 25
Clock Suspend ............................................................ 25
Burst Read/Single Write ............................................ 26
Figure 14, HCS WRITE to READ ........................... 26
Figure 15, Terminating a Write Burst................... 26
Figure 16, Power-Down ........................................ 26
Figure 17, Clock Suspend During Write Burst..... 26
Figure 18, Clock Suspend During Read Burst ..... 26
TRUTH TABLE 3 – CKE ......................................... 27
TRUTH TABLE 4 – Current State Bank
n;
Command to Bank
n
........................................... 28
TRUTH TABLE 5 – Current State Bank
n;
Command to Bank
m
.......................................... 29
FLASH MEMORY .......................................................... 30
FUNCTIONAL DESCRIPTION..................................... 30
Flash Command Sequences ........................................ 30
Hardware Command Sequence (HCS) .................... 30
Software Command Sequence (SCS) ....................... 30
Table 4 Software Code to Program Data Value
1234h to Address 0000h Using SCS.................... 31
Memory Architecture................................................... 31
Protected Blocks......................................................... 31
Command Execution Logic (CEL) ............................ 31
Internal State Machine (ISM).................................... 32
ISM Status Register .................................................... 32
Output (READ) Operations.......................................... 32
Memory Array............................................................. 32
Status Register ............................................................ 32
Device Configuration Register .................................. 32
Figure 19, 2 Meg x 32 Memory Address Map....... 33
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
64Mb: x16, x 32 SyncFlash Memory
MT28S4M16B1LC_3.fm - Rev 11/02
4
PRELIMINARY
64Mb: x16, x32
SYNCFLASH MEMORY
Figure 20, 4 Meg x 16 Memory Address Map........33
Input Operations ...........................................................33
Memory Array..............................................................33
Command Execution ....................................................34
Status Register .............................................................34
Device Configuration..................................................34
Program Sequence ......................................................34
Erase Sequence ...........................................................35
PROGRAM and ERASE NVMODE Register ...............35
Block Protect/Unprotect Sequence...........................35
Device Protect Sequence............................................36
Chip Initialize Sequence.............................................36
Disable LCR Sequence................................................36
Reset/Power-Down Mode ............................................36
Error Handling...............................................................37
PROGRAM/ERASE Cycle Endurance...........................37
Table 5 Status Register Bit Definition ...................38
Table 6 Device Configuration................................39
Table 7 Status Register Codes................................40
Self-Timed Program Sequence..............................41
Complete Program Status-Check Sequence ........41
Self-Timed Block Erase Sequence.........................42
Complete Block Erase Status-Check Sequence ...42
Block Protect Sequence .........................................43
Complete Block Protect
Status-Check Sequence .......................................43
Device Protect Sequence .......................................44
Complete Block Status-Check Sequence .............44
Device Protect Sequence ...................................... 45
ABSOLUTE MAXIMUM RATINGS*............................. 46
DC ELECTRICAL CHARACTERISTICS AND
OPERATING CONDITIONS................................ 46
I
CC
SPECIFICATIONS AND CONDITIONS.......... 47
CAPACITANCE....................................................... 47
ELECTRICAL CHARACTERISTICS AND RECOM-
MENDED AC OPERATING CONDITIONS ........ 48
AC FUNCTIONAL CHARACTERISTICS ............... 49
PROGRAM and ERASE Timing ............................. 50
Timing Diagrams
INITIALIZE AND LOAD MODE REGISTER
(RP# CONTROL) .................................................. 51
INITIALIZE AND LOAD MODE REGISTER
(FCS CONTROL).................................................. 52
CLOCK SUSPEND MODE ..................................... 53
READ....................................................................... 54
READ – ALTERNATING BANK
READ ACCESSES ................................................. 55
READ – FULL-PAGE BURST ................................. 56
READ – DQM OPERATION ................................... 57
PROGRAM/ERASE
(Bank
a
followed by READ to Bank
a)................
58
PROGRAM/ERASE
(Bank
a
followed by READ to Bank
b)................
59
Package Drawings
86-Pin Plastic TSOP (400 mil) ............................... 60
90-Ball FBGA .......................................................... 61
Revision History ........................................................... 62
64Mb: x16, x 32 SyncFlash Memory
MT28S4M16B1LC_3.fm - Rev 11/02
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
stm32/stm8
京公网安备 11010802033920号
EEWORLD
