531NB1286M00DGR datasheet, PDF

Datasheet> All Categories > Passive components> oscillator> 531NB1286M00DGR

531NB1286M00DGR: DescriptionLVDS Output Clock Oscillator, 1286MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

531NB1286M00DGR Overview

LVDS Output Clock Oscillator, 1286MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531NB1286M00DGR Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
package instruction	ROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Code	unknown
Other features	TAPE AND REEL
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	20%
JESD-609 code	e4
Manufacturer's serial number	531
Installation features	SURFACE MOUNT
Nominal operating frequency	1286 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVDS
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

Light controlled ultra-low frequency oscillation circuit diagram

Relay and contactor working status indication circuit c

TVP component type overvoltage protection circuit

TDA2822 wireless headset circuit diagram

8-bit binary serial addition and subtraction circuit

Audible and visual metronome circuit

as3933 packaging problem: A novice PCB designer encountered a problem when drawing the package. The AS3933 16-pin tssop package has 16 pins, but the official website says it has 20 pins, as shown in the following figureShould ...; 那片红 PCB Design

How to determine whether the received data is a command or data when FPGA controls the data transmission and reception of the network card chip: I use FPGA to control the network card chip to make a data transmission and reception device, but how can I make FPGA start sending data? Specifically, FPGA starts sending data when it receives a comm...; yyj807 Test/Measurement

DIY Electronic Load: It is troublesome to make a power supply without a load. So I thought of DIY an electronic load.The initial idea is to use STM32F103RCT6 because it has two DACs and can carry two loads. Its ADC and DA...; dontium DIY/Open Source Hardware

Bootloader reset parameter setting problem: I have a small question, 44b0, why does some tutorials say PCONA is reset to 0x1ff? The chip manual given by the seller says it is 0x3ff, and the other ports are also different from the manual. What s...; fdsa235236 Embedded System

Question about speed loop integral parameters: Recently, when debugging a machine tool with a large load, jitter lines appeared on the surface of the workpiece. At first, I suspected that the gain was too small. Later, after increasing the gain by...; eeleader-mcu Industrial Control Electronics

A video of former Finance Minister Lou Jiwei talking about 5G: https://vdn.vzuu.com/HD/65351dea-0353-11ec-93e2-76325306413b-v4_t111-viw3OTo2pM.mp4?disable_local_cache=1auth_key=1632379763-0-0-29fb633d3e10a507298a6721a9b2125df=mp4bu=http-comexpiration=1632379763v=...; freebsder RF/Wirelessly

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components