CMOS DUAL SyncFIFO™
DUAL 256 x 18
DUAL 512 x 18
DUAL 1,024 x 18
DUAL 4,096 x 18
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
IDT72805LB
IDT72815LB
IDT72825LB
IDT72845LB
FEATURES:
•
•
•
•
•
•
•
•
•
The IDT72805LB is equivalent to two IDT72205LB 256 x 18 FIFOs
The IDT72815LB is equivalent to two IDT72215LB 512 x 18 FIFOs
The IDT72825LB is equivalent to two IDT72225LB 1,024 x 18 FIFOs
The IDT72845LB is equivalent to two IDT72245LB 4,096 x 18 FIFOs
Offers optimal combination of large capacity (8K), high speed,
design flexibility, and small footprint
Ideal for the following applications:
- Network switching
- Two level prioritization of parallel data
- Bidirectional data transfer
- Bus-matching between 18-bit and 36-bit data paths
- Width expansion to 36-bit per package
- Depth expansion to 8,192 words per package
10ns read/write cycle time, 6.5ns access time
IDT Standard or First Word Fall Through timing
Single or double register-buffered Empty and Full Flags
•
•
•
•
•
•
•
•
•
Easily expandable in depth and width
Asynchronous or coincident Read and Write clocks
Asynchronous or synchronous programmable Almost-Empty
and Almost-Full flags with default settings
Half-Full flag capability
Output Enable puts output data bus in high-impedance state
High-performance submicron CMOS technology
Available in the 128-pin Thin Quad Flatpack (TQFP). Also
available for the IDT72805LB/72815LB/72825LB, in the 121-lead,
16 x 16 mm plastic Ball Grid Array (PBGA)
Industrial temperature range (–40°C to +85°C) is available
°
°
Green parts available, see ordering information
The IDT72805LB/72815LB/72825LB/72845LB are dual 18-bit-wide syn-
chronous (clocked) First-in, First-out (FIFO) memories. One dual IDT72805LB/
DESCRIPTION:
FUNCTIONAL BLOCK DIAGRAM
WCLKA
WENA
DA
0
-DA
17
HF A/(WXOA)
F F A/IR
P AEA
A
EF A/
OR
A
WCLKB
L DA PAFA
WENB
DB0-DB17
L DB
INPUT
REGISTER
OFFSET
REGISTER
INPUT
REGISTER
OFFSET
REGISTER
F F B/IRB
P AF B
EF B/ORB
P AEB
HF B/(WXOB)
WRITE
CONTROL
LOGIC
FLAG
LOGIC
RAM
ARRAY
256 x 18
512 x 18
1,024 x 18
4,096 x 18
WRITE
CONTROL
LOGIC
FLAG
LOGIC
RAM
ARRAY
256 x 18
512 x 18
1,024 x 18
4,096 x 18
WRITE
POINTER
F LA
WXIA
(HF
A)/WXOA
RXIA
RXOA
RSA
READ
POINTER
READ
CONTROL
LOGIC
WRITE
POINTER
READ
POINTER
READ
CONTROL
LOGIC
EXPANSION
LOGIC
OUTPUT
REGISTER
EXPANSION
LOGIC
OUTPUT
REGISTER
RESET
LOGIC
RESET
LOGIC
OEA
QA
0
-QA
17
RCLKA
RENA
RSB
RXOB
RXIB
(HF
B)/WXOB
WXIB
F LB
OEB
QB
0
-QB
17
RCLKB
RENB
3139 drw 01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
©
2018 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
MARCH 2018
DSC-3139/10
IDT72805LB/72815LB/72825LB/72845LB CMOS Dual SyncFIFO
TM
256 x 18, 512 x 18, 1,024 x 18, and 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
DESCRIPTION (Continued)
72815LB/72825LB/72845LB device is functionally equivalent to two
IDT72205LB/72215LB/72225LB/72245LB FIFOs in a single package with all
associated control, data, and flag lines assigned to independent pins. These
devices are very high-speed, low-power First-In, First-Out (FIFO) memories
with clocked read and write controls. These FIFOs are applicable for a wide
variety of data buffering needs, such as optical disk controllers, Local Area Networks
(LANs), and interprocessor communication.
Each of the two FIFOs contained in these devices has an 18-bit input and
output port. Each input port is controlled by a free-running clock (WCLK), and
an input enable pin (WEN). Data is read into the synchronous FIFO on every
clock when
WEN
is asserted. The output port of each FIFO bank is controlled
by another clock pin (RCLK) and another enable pin (REN). The Read Clock
can be tied to the Write Clock for single clock operation or the two clocks can
run asynchronous of one another for dual-clock operation. An Output Enable
pin (OE) is provided on the read port of each FIFO for three-state control of the
output.
The synchronous FIFOs have two fixed flags, Empty Flag/Output Ready
(EF/OR) and Full Flag/Input Ready (FF/IR), and two programmable flags,
Almost-Empty (PAE) and Almost-Full (PAF). The offset loading of the program-
mable flags is controlled by a simple state machine, and is initiated by asserting
the Load pin (LD). A Half-Full flag (HF) is available for each FIFO that is
implemented as a single device configuration.
There are two possible timing modes of operation with these devices: IDT
Standard mode and First Word Fall Through (FWFT) mode.
In IDT Standard Mode, the first word written to an empty FIFO will not
appear on the data output lines unless a specific read operation is performed.
A read operation, which consists of activating
REN
and enabling a rising RCLK
edge, will shift the word from internal memory to the data output lines.
In FWFT mode, the first word written to an empty FIFO is clocked directly
to the data output lines after three transitions of the RCLK signal. A
REN
does
not have to be asserted for accessing the first word.
These devices are depth expandable using a daisy-chain technique or First
Word Fall Through (FWFT) mode. The
XI
and
XO
pins are used to expand the
FIFOs. In depth expansion configuration,
FL
is grounded on the first device and
set to HIGH for all other devices in the Daisy Chain.
The IDT72805LB/72815LB/72825LB/72845LB are fabricated using high-
speed submicron CMOS technology.
PIN CONFIGURATIONS
PIN 1
A
WCLKA
DA3
DA1
DA0
DB13
DB16
RCLKB
LDB
RSB
QB17
QB16
B
PAFA
DA4
WENA
DA2
DB12
DB15
RENB
OEB
EFB
QB15
QB14
C
FFA
RXIA
WXIA
DA5
DB14
DB11
GND
DB17
GND
QB13
QB11
D
RXOA
QA0
QA2
FLA
DB8
DB10
DB7
VCC
QB12
QB10
QB8
E
QA1
QA4
QA3
WXOA/
HFA
PAEA
DB9
DB6
VCC
VCC
QB9
QB7
F
QA5
QA6
GND
VCC
GND
GND
GND
VCC
GND
QB6
QB5
G
QA7
QA9
VCC
VCC
DA6
DA9
PAEB
WXOB/
HFB
QB3
QB4
QB1
H
QA8
QA10
QA12
VCC
DA7
DA10
DA8
FLB
QB2
QB0
RXOB
J
QA11
QA13
GND
DA17
GND
DA11
DA14
DB5
WXIB
RXIB
FFB
K
QA14
QA15
EFA
OEA
RENA
DA15
DA12
DB2
WENB
DB4
PAFB
L
QA16
QA17
RSA
LDA
RCKLA
DA16
DA13
DB0
DB1
DB3
WCLKB
1
2
3
4
5
6
7
8
9
10
11
3139 drw 02
NOTE:
1. The PBGA is only available for the IDT72805LB/72815LB/72825LB in the 15 or 25 ns speed grade.
PBGA (BG121, order code: BG)
TOP VIEW
2
IDT72805LB/72815LB/72825LB/72845LB CMOS Dual SyncFIFO
TM
256 x 18, 512 x 18, 1,024 x 18, and 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN CONFIGURATIONS (Continued)
INDEX
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
WXIA
WENA
WCLKA
FLA
PAEA
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA8
DA9
DA10
DA11
DA12
DA13
DA14
DA15
DA16
DA17
GND
RCLKA
RENA
QB0
QB1
GND
QB2
QB3
V
CC
QB4
GND
QB5
QB6
QB7
QB8
GND
QB9
QB10
V
CC
QB11
QB12
GND
QB13
QB14
V
CC
QB15
GND
QB16
QB17
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
V
CC
PAFA
RXIA
FFA
WXOA/HFA
RXOA
QA0
QA1
GND
QA2
QA3
V
CC
QA4
GND
QA5
QA6
QA7
QA8
GND
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
PAEB
FLB
WCLKB
WENB
WXIB
V
CC
PAFB
RXIB
FFB
WXOB/HFB
RXOB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
LDA
OEA
RSA
V
CC
GND
EFA
QA17
QA16
GND
QA15
V
CC
QA14
QA13
GND
QA12
QA11
V
CC
QA10
QA9
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
DB16
DB17
GND
RCLKB
RENB
LDB
OEB
RSB
V
CC
GND
EFB
3139 drw 02a
TQFP (PK128, order code: PF)
TOP VIEW
3
IDT72805LB/72815LB/72825LB/72845LB CMOS Dual SyncFIFO
TM
256 x 18, 512 x 18, 1,024 x 18, and 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN DESCRIPTION
Symbol
DA
0
–DA
17
DB
0
-DB
17
RSA
RSB
WCLKA
WCLKB
WENA
WENB
RCLKA
RCLKB
RENA
RENB
OEA
OEB
LDA
LDB
FLA
FLB
Name
Data Inputs
Reset
Write Clock
Write Enable
Read Clock
Read Enable
Output Enable
Load
I/O
I
I
I
I
I
I
I
I
Data inputs for an 18-bit bus.
When
RS
is set LOW, internal read and write pointers are set to the first location of the RAM array,
FF
and
PAF
go HIGH, and
PAE
and
EF
go LOW. A reset is required before an initial WRITE after power-up.
When
WEN
is LOW, data is written into the FIFO on a LOW-to-HIGH transition of WCLK, if the FIFO is not full.
When
WEN
is LOW, data is written into the FIFO on every LOW-to-HIGH transition of WCLK. When
WEN
is
HIGH, the FIFO holds the previous data. Data will not be written into the FIFO if the
FF
is LOW.
When
REN
is LOW, data is read from the FIFO on a LOW-to-HIGH transition of RCLK, if the FIFO is not empty.
When
REN
is LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. When
REN
is HIGH,
the output register holds the previous data. Data will not be read from the FIFO if the
EF
is LOW.
When
OE
is LOW, the data output bus is active. If
OE
is HIGH, the output data bus will be in a high-impedance
state.
When
LD
is LOW, data on the inputs D0–D11 is written to the offset and depth registers on the LOW-to-HIGH
transition of the WCLK, when
WEN
is LOW. When
LD
is LOW, data on the outputs Q0–Q11 is read from the
offset and depth registers on the LOW-to-HIGH transition of the RCLK, when
REN
is LOW.
In the single device or width expansion configuration,
FL
together with
WXI
and
RXI
determine if the mode is
IDT Standard mode or First Word Fall Through (FWFT) mode, as well as whether the
PAE/PAF
flags are
synchronous or asynchronous. (See Table I.) In the Daisy Chain Depth Expansion configuration,
FL
is grounded
on the first device (first load device) and set to HIGH for all other devices in the Daisy Chain.
In the single device or width expansion configuration,
WXI
together with
FL
and
RXI
determine if the mode is
IDT Standard mode or FWFT mode, as well as whether the
PAE/PAF
flags are synchronous or asynchronous.
(See Table 1.) In the Daisy Chain Depth Expansion configuration,
WXI
is connected to
WXO
(Write Expansion
Out) of the previous device.
In the single device or width expansion configuration,
RXI
together with
FL
and
WXI,
determine if the mode is
IDT Standard mode or FWFT mode, as well as whether the
PAE/PAF
flags are synchronous or asynchronous.
(See Table 1.) In the Daisy Chain Depth Expansion configuration,
RXI
is connected to
RXO
(Read Expansion
Out) of the previous device.
In the IDT Standard mode, the
FF
function is selected
FF
indicates whether or not the FIFO memory is full. In
the FWFT mode, the
IR
function is selected.
IR
indicates whether or not there is space available for writing to
the FIFO memory.
In the IDT Standard mode, the
EF
function is selected.
EF
indicates whether or not the FIFO memory is empty.
In FWFT mode, the
OR
function is selected.
OR
indicates whether or not there is valid data available at the
outputs.
When
PAE
is LOW, the FIFO is almost-empty based on the offset programmed into the FIFO. The default
offset at reset is 31 from empty for IDT72805LB, 63 from empty for IDT72815LB, and 127 from empty for
IDT72825LB/72845LB.
When
PAF
is LOW, the FIFO is almost-full based on the offset programmed into the FIFO. The default offset
at reset is 31 from full for IDT72805LB, 63 from full for IDT72815LB, and 127 from full for IDT72825LB/72845LB.
In the single device or width expansion configuration, the device is more than half full when
HF
is LOW. In the
depth expansion configuration, a pulse is sent from
WXO
to
WXI
of the next device when the last location in
the FIFO is written.
In the depth expansion configuration, a pulse is sent from
RXO
to
RXI
of the next device when the last location
in the FIFO is read.
Data outputs for an 18-bit bus.
+5V power supply pins.
Ground pins.
Description
First Load
I
WXIA
WXIB
Write Expansion
Input
I
RXIA
RXIB
Read Expansion
Input
I
FFA/IRA
FFB/IRB
EFA/ORA
EFB/ORB
PAEA
PAEB
PAFA
PAFB
WXOA/HFA
WXOB/HFB
RXOA
RXOB
QA
0
–QA
17
QB
0
-QB
17
V
CC
GND
Full Flag/
Input Ready
Empty Flag/
Output Ready
Programmable
Almost-Empty flag
Programmable
Almost-Full flag
Write Expansion
Out/Half-Full Flag
Read Expansion
Out
Data Outputs
Power
Ground
O
O
O
O
O
O
O
4
IDT72805LB/72815LB/72825LB/72845LB CMOS Dual SyncFIFO
TM
256 x 18, 512 x 18, 1,024 x 18, and 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS
Symbol
V
TERM
T
STG
I
OUT
Rating
Terminal Voltage
with respect to GND
Storage
Temperature
DC Output Current
Commercial
–0.5 to +7.0
–55 to +125
–50 to +50
Unit
V
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
V
CC
GND
V
IH
V
IL
(1)
T
A
T
A
Parameter
Supply Voltage (Com’l/Ind’l)
Supply Voltage (Com’l/Ind’l)
Input High Voltage (Com’l/Ind’l)
Input Low Voltage (Com’l/Ind’l)
Operating Temperature
Commercial
Operating Temperature
Industrial
Min.
4.5
0
2.0
⎯
0
-40
Typ.
5.0
0
⎯
⎯
⎯
⎯
Max.
5.5
0
⎯
0.8
70
85
Unit
V
V
V
V
°C
°C
°
C
mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 5V ± 10%, T
A
= 0°C to +70°C; Industrial: V
CC
= 5V
±
10%, TA = -40°C to +85°C)
IDT72805LB
IDT72815LB
IDT72825LB
IDT72845LB
Com’l & Ind’l
(1)
t
CLK
= 10, 15, 25 ns
Typ.
—
—
—
—
—
—
Symbol
I
LI
(2)
I
LO
(3)
V
OH
V
OL
I
CC1
(4,5,6)
I
CC2
(4,7)
NOTES:
1.
2.
3.
4.
4.
5.
Parameter
Input Leakage Current (any input)
Output Leakage Current
Output Logic “1” Voltage, I
OH
= –2 mA
Output Logic “0” Voltage, I
OL
= 8 mA
Active Power Supply Current
Standby Current
Min.
–1
–10
2.4
—
—
—
Max.
1
10
—
0.4
100
10
Unit
µA
µA
V
V
mA
mA
Industrial Temperature Range Product for the 15ns speed grade is available as a standard device.
Measurements with 0.4
≤
V
IN
≤
V
CC
.
OE
≥
V
IH,
0.4
≤
V
OUT
≤
V
CC
.
Tested with outputs open (I
OUT
= 0).
RCLK and WCLK toggle at 20 MHZ and data inputs switch at 10 MHz.
For the IDT72805LB/72815LB/72825LB the typical I
CC1
= 2[1.81 + 1.12*f
S
+ 0.02*C
L
*f
S
] (in mA);
for the IDT72845LB the typical I
CC1
= 2[2.85 + 1.30*f
S
+ 0.02*C
L
*f
S
] (in mA).
These equations are valid under the following conditions:
V
CC
= 5V, T
A
= 25°C, f
S
= WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at f
S
/2, C
L
= capacitive load (in pF).
7. All Inputs = V
CC
- 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
(2)
C
OUT
(1,2)
Parameter
(1)
Input
Capacitance
Output
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
10
10
Unit
pF
pF
NOTES:
1. With output deselected, (OE
≥
V
IH
).
2. Characterized values, not currently tested.
5
ADI Reference Circuit
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