White Electronic Designs
High Density FLASH Memory Card
16, 32, 48, 64, 80 MEGABYTE
FEATURES
n
Low cost High Density Linear Flash Card
n
Single 5V Supply
PCMCIA Flash Memory Card
FLF0 Series
- (3V/5V operation is available as an option)
n
Based on Intel 28F640J5 (MLC) Components
n
Fast Read Performance
These higher densities are based on a paging
scheme. By writing a page address to the Configuration
Option Register (address 4000H), an additional page
of memory could be access. The current FLF0 series
supports densities to 80MB: total of 2 pages: page 0 :=
64MB, page 1 := 16MB.
To provide a 16 bit word wide access and to support
PCMCIA standard, devices are paired on the card.
Therefore, the Flash array is structured in 128K word
(256kB) blocks. Write, read and block erase operations
can be performed as either a word or byte wide
operation.
The FLF0 series cards conform with the PC Card 95
Standard supported by PCMCIA and JEIDA, providing
electrical and physical compatibility. The PC Card form
factor offers an industry standard pinout and mechanical
outline, allowing density upgrades without system
design changes.
WEDCs standard cards are shipped with WEDCs
Flash Logo. Cards are also available with blank
housings (no Logo). The blank housings are available
in both, a recessed (for label) or flat housing. Please
contact WEDC sales representative for further
information on Custom artwork.
- 250ns Maximum Access Time
- (200ns optional)
- x8/ x16 Data Interface
- 6µs per Byte Effective Write Time
- Intel Basic Command Set
- Common Flash Interface (CFI)
- Scaleable Command Set
n
PCMCIA compatible
n
32-Byte Write Buffer
n
Cross-Compatible Command Support
n
Power-Down Mode
- Reset, Power Down Registers
n
10,000 Erase Cycles per Block
n
128K word symmetrical Block Architecture
n
PC Card Standard Type II Form Factor
GENERAL DESCRIPTION
WEDCs Flash memory cards FLF0 Series - offer
high density linear Flash memory for code and data
storage, high performance disk emulation, mobile PC
and embedded applications.
The WEDC FLF0 series is based on Intels Multi Level
Cell (MLC) Flash memory technology, providing high
density Flash components at significantly lower cost per
megabyte. MLC technology allows for two bits of
information to be stored in a single cell. This leads to
reduced die size and reduced cost per megabyte.
WEDCs FLF0 series cards are built with Intels 64Mb
components, 28F640J5, with manufacturer/device ID
of 89/15
H
. The FLF0 series is available in standard
densities of 16, 32, 48 and 64MB.
Additionally, WEDCs FLF0 series provides densities
beyond the 64MB density, supported by PCMCIA standard.
June 2003 Rev. 5
ECO #16109
1
White Electronic Designs Corporation (508) 485-4000 www.whiteedc.com
White Electronic Designs
BLOCK DIAGRAM
N x 28F640J5
Device Pair (N/2 - 1)
CLn
CH0
Device (N-1)
Device (N-2)
(B26)
A1-A23
PCMCIA Flash Memory Card
FLF0 Series
+
ADDRESS BUS
(A1-A25)
(A1-A25)
A24, A25, B26
B26, (B27..)
A1-A25
ADDRESS
BUFFER
D5-D0=Page Number (PN)
SRes
D7
M Res
WRi
RDi
CHn
Qn
Device Pair 1
CH0
Device 3
Device 2
CL1
CH0
CLn
CL0
Q2
Q0
Ctrl
Ai
LvReq
D6
D5
- Page Number (PN) -
D4
D3
D2
D1
D0
Configuration Option Register: A=4000h (Read/Write)
WE
OE
control
logic
CE2
CE1
REG
SR Clr
Reg Clr
ADDRESS Register NAME
4008h
4006h
4004h
4002h
Config. and Status Reg.
4000h
Configuration Option Register
At/Reg enable
Device Pair 0
CL0
CH0
Device 1
Device 0
4000h
Management
Registers
DATA
BUS
Q8-Q15
DATA
BUS
Q0-Q7
0000h
attrib. mem
CIS
E²PROM 2kB
control
Q0-Q7
I/O buffer
DATA
BUS
D8
-
D15
DATA
BUS
D0
-
D7
A0
Reset
220k
reset circuit
C
M Res
SR Clr
Reg Clr
Vcc
10k
D0 - D15
CD1
CD2
Vcc
GND
WAIT
R/BUSY
VS1
VS2
BVD1
BVD2
Vpp2
Vpp1
N.C.
N.C.
R/B1
R/B0
OPEN
OPEN
10k
Vcc
OPEN
R/B(N-1)
Vcc
Configuration Option Register: ADRS=4000h
Read/Write
SRes
D7
D7
LvReq
- Page Number (PN) -
D2
D1
D0
D6
D5
D4
D3
Soft Reset, active High
1=Reset State
0=End Reset State
LevelReq (not supported)
Configuration index
D5-D1
reserved
D0
Page Number Config. (PN)
D6
D5-D0
Power On default =0
Configuration Status Register: ADRS=4002h
Read/Write
reserved
PwrDwn
reserved
D7
D6
D5
D4
D3
D2
D1
D0
D2
Power Down; active High
1 = Place all memory devices in power down mode
0 = normal operation
Power On default=0
CE1, CE2, OE, WE, Reg: pull up
typ 100k
A0, A25, Reset:
pull down typ 100k
R/Busy - Open Drain output (require pull up on host)
Manufacturer ID
Device ID
Intel
89
H
15
H
28F640J5
FLF0 Flash Card
based on Strata Flash 28F640J5
White Electronic Designs Corporation Marlborough, MA (508) 485-4000
2
White Electronic Designs
P
INOUT
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Signal name
GND
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
CE
1
A
10
OE
A
11
A
9
A
8
A
13
A
14
WE
RDY/BSY
V
CC
V
PP
1
A
16
A
15
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
WP
GND
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
I
O
Function
Ground
Data bit 3
Data bit 4
Data bit 5
Data bit 6
Data bit 7
Card enable 1
Address bit 10
Output enable
Address bit 11
Address bit 9
Address bit 8
Address bit 13
Address bit 14
Write Enable
Ready/Busy
Supply Voltage
Prog. Voltage
Address bit 16
Address bit 15
Address bit 12
Address bit 7
Address bit 6
Address bit 5
Address bit 4
Address bit 3
Address bit 2
Address bit 1
Address bit 0
Data bit 0
Data bit 1
Data bit 2
Write Potect
Ground
Active
Pin
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
PCMCIA Flash Memory Card
FLF0 Series
LOW
LOW
LOW
LOW (1)
NC
I
I
I
I
I
I
I
I
I
I
I
I/O
I/O
I/O
O
HIGH
Signal name
GND
CD
1
DQ
11
DQ
12
DQ
13
DQ
14
DQ
15
CE
2
VS
1
RFU
RFU
A
17
A
18
A
19
A
20
A
21
V
CC
V
PP
2
A
22
A
23
A
24
A
25
VS
2
RST
Wait
RFU
REG
BVD
2
BVD
1
DQ
8
DQ
9
DQ
10
CD
2
GND
I/O
O
I/O
I/O
I/O
I/O
I
I
O
I
I
I
I
I
I
I
I
I
O
I
O
I
O
O
I/O
I/O
O
O
Function
Ground
Card Detect 1
Data bit 11
Data bit 12
Data bit 13
Data bit 14
Data bit 15
Card Enable 2
Voltage Sense 1
Reserved
Reserved
Address bit 17
Address bit 18
Address bit 19
Address bit 20
Address bit 21
Supply Voltage
Prog. Voltage
Address bit 22
Address bit 23
Address bit 24
Address bit 25
Voltage Sense 2
Card Reset
Extended Bus cycle
Reserved
Attrib Mem Select
Bat. Volt. Detect 2
Bat. Volt. Detect 1
Data bit 8
Data bit 9
Data bit 10
Card Detect 2
Ground
Active
LOW
LOW
NC (2)
NC
NC
HIGH
Low (3)
(3)
(3)
LOW
Notes:
1. RDY/BSY signal is an Open drain type output, pull-up resistors are required on the host side.
2. VS
1
is connected to GND for 3.3V/5V cards and N.C. for 5V only cards.
3. Wait, BVD
1
and BVD
2
are internally connected to V
CC
by resistors for compatibility.
MECHANICAL
1.0mm 0.05
0.039’
1.6mm
0.063”
0.05
85.6mm
3.370”
0.20
3.0mm
MIN.
Substrate area
54.0mm
2.126”
0.10
Pin #35
1.0mm 0.05
0.039’
Pin #1
10.0mm MIN.
0.400”
Interconnect area
3.3mm
0.130”
0.05”
5.0mm MAX.
0.197”
3
White Electronic Designs Corporation (508) 485-4000 www.whiteedc.com
White Electronic Designs
Symbol
A
0
- A
25
DQ
0
- DQ
15
CE
1
, CE
2
OE
WE
RDY/BSY
Type
INPUT
INPUT/OUTPUT
INPUT
INPUT
INPUT
OUTPUT
Name and Function
PCMCIA Flash Memory Card
FLF0 Series
C
ARD
S
IGNAL
D
ESCRIPTION
ADDRESS INPUTS:
A
0
through A
25
enable direct addressing of up to 64MB of memory on the
card. Signal A
0
is not used in word access mode. A
25
is the most significant bit
DATA INPUT/OUTPUT:
DQ
0
THROUGH DQ
15
constitute the bi-directional databus. DQ
15
is the MSB.
CARD ENABLE 1 AND 2:
CE
1
enables even byte accesses, CE
2
enables odd byte accesses.
Multiplexing A
0
, CE
1
and CE
2
allows 8-bit hosts to access all data on DQ
0
- DQ
7
(see truth table).
OUTPUT ENABLE:
Active low signal gating read data from the memory card.
WRITE ENABLE:
Active low signal gating write data to the memory card.
READY/BUSY OUTPUT:
Indicates status of internally timed erase or program algorithms. A high
output indicates that the card is ready to accept accesses. A low output indicates that one or more
devices in the memory card are busy with internally timed erase or write activities.
CARD DETECT 1 and 2:
Provide card insertion detection. These signals are internally connected
to ground on the card. The host shall monitor these signals to detect card insertion (pulled-up on
host side).
WRITE PROTECT:
Write protect reflects the status of the Write Protect switch on the memory
card. WP set to high = write protected, providing internal hardware write lockout to the Flash
array. If card does not include optional write protect switch, this signal will be pulled low internally
indicating write protect = off.
PROGRAMMING VOLTAGES:
Not connected for 5V only card.
CARD POWER SUPPLY:
5.0V for all internal circuitry
CARD GROUND
INPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
ATTRIBUTE MEMORY SELECT :
Active low signal, enables access to attribute memory space,
occupied by the Card Information Structure (CIS) and Card Registers.
RESET:
Active high signal for placing card in Power-on default state. Reset can be used as a
Power-Down control for the memory array.
WAIT:
This signal is pulled high internally for compatibility. No wait states are generated.
BATTERY VOLTAGE DETECT:
These signals are pulled high to maintain SRAM card compatibility.
VOLTAGE SENSE:
Notifies the host socket of the cards V
CC
requirements. VS
1
and VS
2
are
open to indicate a 5V card .
RESERVED FOR FUTURE USE
NO INTERNAL CONNECTION TO CARD:
pin may be driven or left floating
CD
1
, CD
2
OUTPUT
WP
OUTPUT
V
PP
1
, V
PP
2
V
CC
GND
REG
RST
WAIT
BVD
1
, BVD
2
VS
1
, VS
2
RFU
NC
N.C.
F
UNCTIONAL
T
RUTH
T
ABLE
READ function
Function Mode
Standby Mode
Byte Access (8 bits)
Word Access (16 bits)
Odd-Byte Only Access
WRITE function
Standby Mode
Byte Access (8 bits)
Word Access (16 bits)
Odd-Byte Only Access
H
H
H
L
L
H
L
L
L
H
X
L
H
X
X
X
H
H
H
H
X
L
L
L
L
X
H
H
H
H
X
X
X
Odd-Byte
Odd-Byte
X
Even-Byte
Odd-Byte
Even-Byte
X
X
L
L
L
L
X
X
X
X
X
X
Even-Byte
X
Even-Byte
X
CE
2
H
H
H
L
L
CE
1
H
L
L
L
H
A
0
X
L
H
X
X
OE
X
L
L
L
L
WE
X
H
H
H
H
REG
X
H
H
H
H
Common Memory
D
15
-D
8
High-Z
High-Z
High-Z
Odd-Byte
Odd-Byte
D
7
-D
0
High-Z
Even-Byte
Odd-Byte
Even-Byte
High-Z
REG
X
L
L
L
L
Attribute Memory
D
15
-D
8
High-Z
High-Z
High-Z
Not Valid
Not Valid
D
7
-D
0
High-Z
Even-Byte
Not Valid
Even-Byte
High-Z
White Electronic Designs Corporation Marlborough, MA (508) 485-4000
4
White Electronic Designs
CARD INTERFACE
The FLF0 series flash card complies with PC Card
standard (PCMCIA, March 1997). While maintaining
PCMCIA compatibility, the FLF0 series card has
integrated special features to extend functionality.
Card has built in 2 control registers:
- Configuration Option Register (COR)
Address = 4000
h
- Configuration and Status Register (CSR)
Address = 4002
h
COR register:
provide a soft reset function (bit D7) and
additional page register (bit D0) to extend card capacity
beyond 64MB.
SReset
As defined by PCMCIA, setting the SReset bit to 1, places
the card in the reset state. During this state all memory
devices are place in power down mode, minimizing
power consumption. Returning this bit to 0 leaves the
reset cycle and place the card in the same condition as
following a power up or hardware reset. This bit must
be cleared to 0, to access any device on the card.
Complete soft reset cycle must consist of a 2 step write
sequence to the SReset bit:
1. Initialization: write 1 to SReset
- reset cycle begin
- memory devices enters Power-Down mode
aborting all operations and clearing all registers.
2. Write 0 to SReset
- Reset cycle ends
- memory devices and registers enters power on
default state
Card can be place in Power Down mode by activating
Reset signal (pin58) or by controlling the bit D2 in
CSR register.
LevlRequest
Not supported
Configuration Index
Configuration Index bits (D0 - D5) are defined to provide
address extension bits -page address, to extend card
capacity beyond 64MB.
PCMCIA Flash Memory Card
FLF0 Series
Only bit D0 is supported:
- D0 set to 0 selects
- D0 set to 1 selects:
page 0
page 1
D0 is set to the value of 0, during power on or
any reset.
CSR register:
provide a power control of memory array.
Only bit D2 is supported; all other bits are dont care
PwrDwn
Writing 1 to PwrDwn bit (D2) forces each memory
device on the card into a reset/power down mode by
asserting all the devices RP# pins. Writing 0 to the bit
returns the array to stand by mode.
Card Information Structure (CIS) contains information
about Registers addressing and Memory structure.
Cards with memory capacity < 64MB do not support
Configuration Index bits.
Notes:
1. Reading from undefined address location or unsupported bits will
return random data.
2. Writing to undefined address location may result in card
malfunctioning due to limited address decoding.
3. See block diagram for more details about control registers.
5
White Electronic Designs Corporation (508) 485-4000 www.whiteedc.com
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