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MC10E196, MC100E196
5V ECL Programmable
Delay Chip
Description
The MC10E/100E196 is a programmable delay chip (PDC)
designed primarily for very accurate differential ECL input edge
placement applications.
The delay section consists of a chain of gates and a linear ramp delay
adjust organized as shown in the logic symbol. The first two delay
elements feature gates that have been modified to have delays
1.25 and 1.5 times the basic gate delay of approximately 80 ps. These
two elements provide the E196 with a digitally-selectable resolution
of approximately 20 ps. The required device delay is selected by the
seven address inputs D[0:6], which are latched on chip by a high signal
on the latch enable (LEN) control.
The FTUNE input takes an analog voltage and applies it to an
internal linear ramp for reducing the 20 ps Least Significant Bit (LSB)
minimum resolution still further. The FTUNE input is what
differentiates the E196 from the E195.
An eighth latched input, D7, is provided for cascading multiple
PDC’s for increased programmable range. The cascade logic allows
full control of multiple PDC’s, at the expense of only a single added
line to the data bus for each additional PDC, without the need for any
external gating.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a 0.01
mF
capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V
BB
should be left open.
The 100 Series contains temperature compensation.
Features
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PLCC−28
FN SUFFIX
CASE 776
MARKING DIAGRAM*
1
MCxxxE196FNG
AWLYYWW
xxx
A
WL
YY
WW
G
= 10 or 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
•
•
•
•
•
•
2.0 ns Worst Case Delay Range
≈20
ps/Delay Step Resolution
Linear Input for Tighter Resolution
>1.0 GHz Bandwidth
On Chip Cascade Circuitry
PECL Mode Operating Range: V
CC
= 4.2 V to 5.7 V
with V
EE
= 0 V
•
NECL Mode Operating Range: V
CC
= 0 V
with V
EE
=
−4.2
V to
−5.7
V
•
Internal Input 50 kW Pulldown Resistors
•
ESD Protection: Human Body Model; > 1 kV,
Machine Model; > 75 V
•
Meets or Exceeds JEDEC Spec EIA/JESD78 IC
•
•
•
•
Latchup Test
Moisture Sensitivity Level: Pb = 1; Pb−Free = 3
For Additional Information, see Application Note
AND8003/D
Flammability Rating: UL 94 V−0 @ 1.125 in,
Oxygen Index: 28 to 34
Transistor Count = 425 devices
Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
November, 2006
−
Rev. 9
1
Publication Order Number:
MC10E196/D
MC10E196, MC100E196
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
D2
Table 1. PIN DESCRIPTION
PIN
FUNCTION
ECL Signal Input
ECL Input Enable (H Forces Q Low)
ECL MUX Select Inputs
ECL Signal Output
ECL Latch Enable
ECL Min Delay Set
ECL Max Delay Set
ECL Cascade Signal
ECL Linear Voltage Input
Reference Voltage Output
Positive Supply
Negative Supply
No Connect
IN/IN
EN
D[0:7]
Q/Q
LEN
SET MIN
SET MAX
CASCADE
FTUNE
V
BB
V
CC
, V
CCO
V
EE
NC
D3
24
D4
23
D5
22
D6
21
D7
20
NC
19
18
17
16
D1
D0
LEN
26
27
28
1
2
3
4
25
FTUNE
NC
V
CC
V
CCO
Q
Q
V
CCO
V
EE
IN
IN
V
BB
MC10E196
MC100E196
15
14
13
12
5
6
7
8
9
10
11
SET MAX
SET MIN
CASCADE
CASCADE
NC
NC EN
Table 2. TRUTH TABLE
EN
EN
LEN
LEN
SETMIN
SETMIN
SETMAX
SETMAX
L
H
L
H
L
H
L
H
Q = IN
Q Logic Low
Pass Through D[0:10]
Latch D[0:10]
Normal Mode
Min Delay Path
Normal Mode
Max Delay Path
FTUNE
* All V
CC
and V
CCO
pins are tied together on the die.
Warning: All V
CC
, V
CCO
, and V
EE
pins must be externally
connected to Power Supply to guarantee proper operation.
Figure 1. Pinout: PLCC−28
(Top View)
V
BB
IN
IN
EN
1
1
0
1
0
1
* 1.5
1
0
1
1
1
0
1
4 GATES
0
1
8 GATES
0
1
16 GATES
0
1
0
1
1
Q
Q
LINEAR
RAMP
* 1.25
V
EE
CASCADE
7 BIT LATCH
LEN
LATCH
D
Q
LEN
SET MIN
SET MAX
CASCADE
CASCADE
D0
D1
D2
D3
D4
D5
D6
D7
* delays are 25% or 50% longer than
*
standard (standard
≈
80 ps)
Figure 2. Logic Diagram
−
Simplified
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2
MC10E196, MC100E196
Table 3. MAXIMUM RATINGS
Symbol
V
CC
V
EE
V
I
I
out
I
BB
T
A
T
stg
q
JA
q
JC
V
EE
T
sol
Parameter
PECL Mode Power Supply
NECL Mode Power Supply
PECL Mode Input Voltage
NECL Mode Input Voltage
Output Current
V
BB
Sink/Source
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
PECL Operating Range
NECL Operating Range
Wave Solder
Pb
Pb−Free
0 lfpm
500 lfpm
Standard Board
PLCC−28
PLCC−28
PLCC−28
Condition 1
V
EE
= 0 V
V
CC
= 0 V
V
EE
= 0 V
V
CC
= 0 V
Continuous
Surge
V
I
V
CC
V
I
V
EE
Condition 2
Rating
8
−8
6
−6
50
100
±
0.5
0 to +85
−65
to +150
63.5
43.5
22 to 26
4.2 to 5.7
−5.7
to
−4.2
265
265
Unit
V
V
V
V
mA
mA
mA
°C
°C
°C/W
°C/W
°C/W
V
V
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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3
MC10E196, MC100E196
Table 4. 10E SERIES PECL DC CHARACTERISTICS
V
CCx
= 5.0 V; V
EE
= 0.0 V (Note 1)
0°C
Symbol
I
EE
V
OH
V
OL
V
IH
V
IL
V
BB
V
IHCMR
I
IH
I
IL
Characteristic
Power Supply Current
Output HIGH Voltage (Note 2)
Output LOW Voltage (Note 2)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
Input HIGH Voltage Common Mode
Range (Differential Configuration) (Note 3)
Input HIGH Current
Input LOW Current
0.5
0.3
3980
3050
3830
3050
3.62
2.2
Min
Typ
130
4070
3210
3995
3285
Max
156
4160
3370
4160
3520
3.74
4.6
150
0.5
0.25
4020
3050
3870
3050
3.65
2.2
Min
25°C
Typ
130
4105
3210
4030
3285
Max
156
4190
3370
4190
3520
3.75
4.6
150
0.3
0.2
4090
3050
3940
3050
3.69
2.2
Min
85°C
Typ
130
4185
3227
4110
3302
Max
156
4280
3405
4280
3555
3.81
4.6
150
Unit
mA
mV
mV
mV
mV
V
V
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary
−0.46
V / +0.06 V.
2. Outputs are terminated through a 50
W
resistor to V
CC
−
2.0 V.
3. V
IHCMR
min varies 1:1 with V
EE
, max varies 1:1 with V
CC
.
Table 5. 10E SERIES NECL DC CHARACTERISTICS
V
CCx
= 0.0 V; V
EE
=
−5.0
V (Note 4)
0°C
Symbol
I
EE
V
OH
V
OL
V
IH
V
IL
V
BB
V
IHCMR
I
IH
I
IL
Characteristic
Power Supply Current
Output HIGH Voltage (Note 5)
Output LOW Voltage (Note 5)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
Input HIGH Voltage Common Mode
Range (Differential Configuration) (Note 6)
Input HIGH Current
Input LOW Current
0.5
0.3
−1020
−1950
−1170
−1950
−1.38
−2.8
Min
Typ
130
−930
−1790
−1005
−1715
Max
156
−840
−1630
−840
−1480
−1.27
−0.4
150
0.5
0.065
−980
−1950
−1130
−1950
−1.35
−2.8
Min
25°C
Typ
130
−895
−1790
−970
−1715
Max
156
−810
−1630
−810
−1480
−1.25
−0.4
150
0.3
0.2
−910
−1950
−1060
−1950
−1.31
−2.8
Min
85°C
Typ
130
−815
−1773
−890
−1698
Max
156
−720
−1595
−720
−1445
−1.19
−0.4
150
Unit
mA
mV
mV
mV
mV
V
V
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary
−0.46
V / +0.06 V.
5. Outputs are terminated through a 50
W
resistor to V
CC
−
2.0 V.
6. V
IHCMR
min varies 1:1 with V
EE
, max varies 1:1 with V
CC
.
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