Make sure the next
Card you purchase
has...
®
BU-61703/61705
Simple System RT (SSRT)
FEATURES
•
Complete Integrated Remote
Terminal Including:
Dual Low-Power 5V Only Transceiver
Complete RT Protocol Logic
•
Supports MIL-STD-1553A/B Notice 2,
STANAG-3838 RT, and
MIL-STD-1760 Stores Management
•
1.0 X 1.0 Inch, 72-pin Package
•
Choice of 5V or 3.3V Logic Power
•
Meets 1553A/McAir Response Time
Requirements
•
Internal FIFO for Burst Mode
Capability on Receive Data
DESCRIPTION
The BU-61703/5 Simple System RT (SSRT) MIL-STD-1553 terminals
provide a complete interface between a simple system and a MIL-
STD-1553 bus. These terminals integrate dual transceiver, protocol
logic, and a FIFO memory for received messages in a 1.0 inch square
ceramic package. The SSRT provides multi-protocol support of MIL-
STD-1553A/B, MIL-STD-1760, McAir, and STANAG-3838.
The SSRT's transceivers are completely monolithic, require only a
+5V supply, and consume low power. There are versions of the sim-
ple system RT available with transceivers trimmed for MIL-STD-1760
compliance, or compatible to McAir standards. As a means of further
reducing power consumption, the SSRT is available in versions with
its logic powered by +3.3V, or +5V. The SSRT can operate with a
choice of clock frequencies of 10, 12, 16, or 20 MHz.
The SSRT incorporates a built-in self-test (BIT). This BIT, which is
processed following power turn-on or after receipt of an Initiate self-
test mode command, provides a comprehensive test of the SSRT's
encoders, decoders, protocol, transmitter watchdog timer, and proto-
col. The SSRT also includes an auto-configuration feature.
The SSRT is ideal for stores and other simple systems that do not
require a microprocessor. To streamline the interface to simple sys-
tems, the SSRT includes an internal 32-word FIFO for received data
words. This serves to ensure that only complete, consistent blocks of
validated data words are transferred to a system.
•
16-bit DMA Interface
•
Auto Configuration Capability
•
Comprehensive Built-In Self-Test
•
Direct Interface to Simple
(Processorless) Systems
•
Selectable Input Clock:
10, 12, 16, or 20 MHz
FOR MORE INFORMATION CONTACT:
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
Technical Support:
1-800-DDC-5757 ext. 7234
©
2000 Data Device Corporation
Data Device Corporation
www.ddc-web.com
2
BU-61703/61705
D1 web-09/02-0
Note: Transformers are external.
55Ω
BUS A
55Ω
TRANSMITTER
INHIBIT
TX_INH
55Ω
BUS B
55Ω
B-3226
B-3227
MSTCLR
TX/RX B
TX/RX B
TRANSCEIVER
B
TX/RX A
B-3226
B-3227
TX/RX A
TRANSCEIVER
A
DATA
BUFFERS
DMA
HANDSAKE
AND
TRANDFER
CONTROL
LOGIC
D15-D0
DTREQ
DTGRT
DTACK
HS FAIL
MEMOE
MEMWR
SYSTEM
DATA
DMA
HANDSAKE
CONTROL
DATA
TRANSFER
CONTROL
CONTROL
INPUTS
AUTO_CFG
BRO_ENA
DUAL
ENCODER
DECODER
AND
RT STATE
LOGIC
L_BRO, T/R, SA4-SA0
WC/MC/CWC4-0
COMMAND
ADDRESS
BUS
ILLEGAL
RTAD4-RTAD0
SRV_RQST
SSFLAG
BUSY
RTACTIVE
INCMD
RT
ADDRESS
RTADP
RT_AD_LAT
RT_AD_ERR
RT
WORD
INPUTS
CLK_IN
GBR
MSG_ERR
RTFAIL
CLOCK
FEQUENCEY
SELECTION
CLK_SEL1
CLK_SEL0
RT
MESSAGE
STATUS
FIGURE 1. BU-61703/5 BLOCK DIAGRAM
TABLE 1. SIMPLE SYSTEM RT SPECIFICATIONS
PARAMETER
ABSOLUTE MAXIMUM RATING
Supply Voltage
•
Logic +5V or +3.3V
•
RAM +5V
•
Transceiver +5V
•
Voltage Input Range for +5V
Powered Logic (BU-61705)
•
Voltage Input Range for +3.3V
Powered Logic (BU-61703)
RECEIVER
Differential Input Resistance
(Notes 1-6)
Differential Input Capacitance
(Notes 1-6)
Threshold Voltage, Transformer
Coupled,
Common Mode Voltage (Note 7)
TRANSMITTER
Differential Output Voltage
•
Direct Coupled Across 35
Ω,
Measured on Bus
•
Transformer Coupled Across
70
Ω,
Measured on Bus
BU-61573(5)XX-XX0 (Note 8)
BU-61573(5)XX-XX2
(Note 8, 9,13)
Output Noise, Differential (Direct
Coupled)
Output Offset Voltage, Transformer
Coupled Across 70 ohms
Rise/Fall Time
BU-61703(5)X3
BU-61703(5)X4
LOGIC
V
IH
All signals except CLK_IN
CLK_IN
V
IL
All signals except CLK_IN
CLK_IN
Schmidt Hysteresis
All signals except CLK_IN
CLK_IN
I
IH
(Vcc=5.25V, V
IN
=Vcc)
I
IH
(Vcc=5.25V, V
IN
=2.7V)
I
IH
(Vcc=3.6V, V
IN
=Vcc)
I
IH
(Vcc=3.6V, V
IH
=2.7V)
I
IL
(Vcc=5.25V, V
IH
=0.4V)
I
IL
(Vcc=3.6V, V
IH
=0.4V)
V
OH
(Vcc=4.5V, V
IH
=2.7V,
V
IL
=0.2V, I
OH
=max)
V
OH
(Vcc=3.0V, V
IH
=2.7V,
V
IL
=0.2V, I
OH
=max)
V
OL
(Vcc=4.5V, V
IH
=2.7V,
V
IL
=0.2V, I
OL
=max)
V
OL
(Vcc=3.0V, V
IH
=2.7V,
V
IL
=0.2V, I
OL
=max)
I
OL
I
OH
C
I
(Input Capacitance)
C
IO
(Bi-directional signal input
capacitance)
MIN
TYP
MAX
UNITS
TABLE 1. SIMPLE SYSTEM RT SPECS. (Cont’d)
PARAMETER
POWER SUPPLY REQUIREMENTS
Voltages/Tolerances
•
+5V Logic (BU-61705) (Note 10)
•
+3.3V Logic (BU-61703) (Note 10)
•
+5V Ch. A, +5, Ch. B (Note 10)
Current Drain
•
BU-61705XX-XX0
•
+5V (Logic, CH A, CH B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
•
BU-61705XX-XX2
•
+5V (Logic, CH A, CH B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
•
BU-61703XX-XX0
•
+5V (CH A, CH B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
•
3.3V (Logic)
•
BU-61703XX-XX2
•
+5V (CH A, CH B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
•
3.3V (Logic)
POWER DISSIPATION
Total Hybrid (Note 11)
•
BU-61705XX-XX0
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
•
BU-61705XX-XX2
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
•
BU-61703XX-XX0
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
•
BU-61703XX-XX2
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
Hottest Die (Note 11)
•
BU-6170XXX-XX0
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
•
BU-6170XXX-XX2
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
MIN
TYP
MAX UNITS
-0.3
-0.3
-0.3
-0.3
-0.3
2.5
6.0
6.0
7.0
6.0
6.0
V
V
V
V
V
KΩ
4.5
3.0
4.75
5.0
3.3
5.0
5.5
3.6
5.25
V
V
V
160
265
370
580
mA
mA
mA
mA
5
0.200
0.860
10
pF
Vp-p
Vpeak
160
276
392
625
mA
mA
mA
mA
6
7
9
Vp-p
18
20
20
22
27
27
10
Vp-p
Vp-p
mV
P
-
P
mV
peak
100
205
310
520
40
mA
mA
mA
mA
mA
-250
150
250
100
216
332
565
40
mA
mA
mA
mA
mA
100
200
150
250
300
300
nsec
nsec
2.1
0.8•Vcc
0.7
0.2•Vcc
0.4
1.0
-10
-350
-10
-350
-350
-350
2.4
2.4
0.4
0.4
3.4
-3.4
50
50
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
V
V
V
V
mA
mA
pF
pF
0.88
1.11
1.33
1.79
0.88
1.17
1.46
2.05
0.69
0.92
1.15
1.60
0.69
0.98
1.28
1.86
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
10
-50
10
-33
-50
-33
0.28
0.51
0.75
1.22
0.28
0.58
0.88
1.48
W
W
W
W
W
W
W
W
Data Device Corporation
www.ddc-web.com
3
BU-61703/61705
D1 web-09/02-0
TABLE 1. SIMPLE SYSTEM RT SPECS. (Cont’d)
PARAMETER
CLOCK INPUT
Frequency
•
Nominal Value
• Default
• Option
• Option
• Option
•
Long Term Tolerance
• 1553A Compliance
• 1553B Compliance
•
Short Term Tolerance, 1 second
• 1553A Compliance
• 1553B Compliance
•
Duty Cycle
1553 MESSAGE TIMING
RT-to-RT Response Timeout
(Note 12)
RT Response Time
(mid-parity to mid-sync) (Note 12)
Transmitter Watchdog Timeout
THERMAL
-1XX, -4XX
-2XX, -5XX
-3XX, -8XX
•
Ceramic Flatpack / Gull Lead
• Thermal Resistance, Junction-to-
Case, Hottest Die (θ
JC
)
• Max Case Temperature
• Operating Junction Temperature
• Storage Temperature
• Lead Temperature (soldering, 10
sec.)
PHYSICAL CHARACTERISTICS
Size
•
Ceramic Flatpack / Gull Lead
Weight
Flatpack/Gull lead package
MIN
TYP
MAX UNITS
NOTES:
Notes 1 through 6 are applicable to the Receiver Differential Resistance
and Differential Capacitance specifications:
(1)
Specifications include both transmitter and receiver (tied together
internally).
Impedance parameters are specified directly between pins
TX/RX A(B) and TX/RX A(B) of the SSRT hybrid.
It is assumed that all power and ground inputs to the hybrid are con-
nected.
The specifications are applicable for both unpowered and powered
conditions.
The specifications assume a 2 volt rms balanced, differential, sinu-
soidal input. The applicable frequency range is 75 kHz to 1 MHz.
Minimum resistance and maximum capacitance parameters are
guaranteed over the operating range, but are not tested.
Assumes a common mode voltage within the frequency range of dc
to 2 MHz, applied to the pins of the isolation transformer on the stub
side (either direct or transformer coupled), and referenced to hybrid
ground. Transformer must be a DDC recommended transformer or
other transformer that provides an equivalent minimum CMRR.
An "X" in one or more of the product type fields indicates that the ref-
erence is applicable to all available product options.
MIL-STD-1760 requires an output of 20 Vp-p minimum on the stub
connection.
16.0
12.0
10.0
20.0
-0.01
-0.10
-0.001
-0.01
40
0.01
0.10
0.001
0.01
60
MHz
MHz
MHz
MHz
%
%
%
%
%
(2)
(3)
(4)
17.5
4
18.5
19.5
7
µs
µs
µs
°C
°C
°C
(5)
660.5
-55
-40
0
+125
+85
+70
(6)
(7)
9
-55
-65
11
125
160
150
+300
°C/W
°C
°C
°C
°C
(8)
(9)
1.0 X 1.0 X 0.155
(25.4 x 25.4 x 3.94)
0.6
(17)
in.
(mm)
oz
(g)
(10) External 10 µF tantalum and 0.1 µF capacitors to ground should be
located as close as possible to Pins 20 and 72, and a 0.1 µF capac-
itor at pin 37.
(11) Power dissipation specifications assume a transformer coupled con-
figuration, with external dissipation (while transmitting) of 0.14 watts
for the active isolation transformer, 0.08 watts for the active bus cou-
pling transformer, 0.45 watts for each of the two bus isolation resis-
tors, and 0.15 watts for each of the two bus termination resistors.
(12) Measured from mid-parity crossing of command word to mid-sync
crossing of RT's status word.
(13) MIL-STD-1760 compliant output voltage not available for
BU-61703/5X4 versions.
Data Device Corporation
www.ddc-web.com
4
BU-61703/61705
D1 web-09/02-0
INTRODUCTION
GENERAL
The BU-61703/5 Simple System RT (SSRT) is a complete MIL-
STD-1553 Remote Terminal (RT) bus interface unit. Contained in
this hybrid are a dual transceiver and Manchester II
encoder/decoder, and MIL-STD-1553 Remote Terminal (RT) pro-
tocol logic. Also included are built-in self-test capability and a par-
allel subsystem interface. The subsystem interface includes a 12-
bit address bus and a 16-bit data bus that operates in a 16-bit
DMA handshake transfer configuration. The local bus and associ-
ated control signals may be operated from either +5 volt or +3.3
volt power.
The transceiver front end of the BU-61703/5 is implemented by
means of low-power monolithic technology. The transceiver
requires only a single +5 V voltage source. The voltage source
transmitters provide superior line driving capability for long cables
and heavy amounts of bus loading. In addition, the monolithic
transceivers provide a minimum stub voltage level of 20 volts
peak-to-peak transformer coupled, making the BU-61703/5 suit-
able for MIL-STD-1760 applications.
The receiver sections of the BU-61703/5 are fully compliant with
MIL-STD-1553B in terms of front-end overvoltage protection,
threshold, and bit-error rate.
The BU-61703/5 implements all MIL-STD-1553 message formats,
including all 13 MIL-STD 1553 dual redundant mode codes. Any
subset of the possible 1553 commands (broadcast, T/R bit, sub-
address, word count/mode code) may be optionally illegalized by
means of an external PROM, PLD, or RAM. An extensive amount
of message validation is performed for each message received.
Each word received is validated for correct sync type and sync
encoding, Manchester II encoding, parity, and bit count. All mes-
sages are verified to contain a legal, defined command word and
correct word count. If the BU-61703/5 is the receiving RT in an RT-
to-RT transfer, it verifies that the T/R bit of the transmit command
word is logic "1" and that the transmitting RT responds in time and
contains the correct RT address in its Status Word.
The BU-61703/5 may be operated from a 10, 12, 16, or 20 MHz
clock input. For any clock frequency, the decoder samples incom-
ing data on
both
edges of the clock input. This oversampling, in
effect, provides for a sampling rate of twice the input clocks' fre-
quency. Benefits of the higher sampling rate include a wider toler-
ance for zero-crossing distortion and improved bit error rate per-
formance.
The BU-61703/5 includes a hardwired RT address input. This
includes 5 address lines, an address parity input, and an address
parity error output. The RT address can also be latched by means
of a latching input signal.
The BU-61703/5 supports command illegalization. Commands
may be illegalized by asserting the input signal ILLEGAL active
low within approximately 2 µs after the mid-parity bit zero-crossing
of the received command word. Command words may be illegal-
ized as a function of broadcast, T/R bit, subaddress, word count,
and/or mode code.
Data Device Corporation
www.ddc-web.com
5
An internal Built-in-Test (BIT) Word register is updated at the end
of each message. The contents of the BIT Word Register are
transmitted in response to a Transmit BIT Word Mode Command.
The BU-61703/5 provides a number of real-time output signals.
These various signals provide indications of message in progress,
valid received message, message error, handshake fail, loop-test
fail or transmitter timeout.
The BU-61703/5 includes standard DMA handshake signals
(Request, Grant, and Acknowledge) as well as transfer control out-
puts (MEMOE and MEMWR). The DMA interface operates in a 16-
bit mode, supporting word-wide transfers.
The SSRT's system interface allows the BU-61703/5 to be inter-
faced directly to a simple system that doesn't include a micro-
processor. This provides a low-cost 1553 interface for A/D and D/A
converters, switch closures, actuators, and other discrete I/O sig-
nals.
The BU-61703/5 has an internal FIFO for received data words.
This 32-word deep FIFO may be used to allow the BU-61703/5 to
transfer its data words to the local system in burst mode. Burst
mode utilizes the FIFO by transferring data to the local bus at a
rate of one data word every three clock cycles. Burst mode nego-
tiates only once for use of the subsystem bus. Negotiation is per-
formed only after all 1553 data words have been received and val-
idated. In non-burst mode, the BU-61703/5 will negotiate for the
local bus after every received data word. The data word transfer
period is three clock cycles for each received 1553 data word.
The BU-61703/5 may also be used in a shared RAM interface con-
figuration. By means of tri-state buffers and a small amount of
"glue" logic, the BU-61703/5 will store Command Words and
access Data Words to/from dedicated "mailbox" areas in a shared
RAM for each broadcast / T/R bit / subaddress / mode code.
ADDRESS MAPPING
A typical addressing scheme for the BU-61703/5 12-bit address
bus could be as follows:
A11:
A10:
A9-A5:
A4-A0:
BROADCAST/OWNADDRESS
TRANSMIT/RECEIVE
SUBADDRESS 4-0
WORD COUNT/MODE CODE 4-0
This method of address mapping provides for a "mailbox" alloca-
tion scheme for the storage of data words. The 12 address outputs
may be used to map into 4K words of processor address space.
The BU-61703/5's addressing scheme maps messages in terms
of broadcast/ownaddress, transmit/receive, subaddress, and
word/count mode code. A 32-word message block is allocated for
each T/R-subaddress.
For non-mode code messages, the Data Words to be transmitted
or received are accessed from (to) relative locations
0 through 31 within the respective message block. For the
MIL-STD-1553B Synchronize with data, Selected transmitter shut-
BU-61703/61705
D1 web-09/02-0
Motor Drive Control（Motor Control）
京公网安备 11010802033920号
EEWORLD
