HDMP-1636AG
Gigabit Ethernet and Fibre Channel SerDes ICs
Data Sheet
HDMP-1636AG Transceiver
HDMP-1646AG Transceiver
HDMP-T1636AG Transceiver
Description
The HDMP-1636AG/46AG/T1636AG transceiver is
a single integrated circuit packaged in a plastic QFP
package. It provides a low-cost, low-power physical
layer solution for 1250 MBd Gigabit Ethernet, 1062.5
MBd Fibre Channel, and proprietary link interfaces.
It provides complete Serialize/Deserialize (SerDes)
for copper transmission, incorporating the Gigabit
Ethernet/Fibre Channel transmit and receive
functions into a single device.
This chip is used to build a high speed interface (as
shown in Figure 1) while minimizing board space,
power and cost. It is compatible with the
IEEE 802.3z specification.
The transmitter section accepts 10-bit wide parallel
TTL data and serializes this data into a high speed
serial data stream. The parallel data is expected
to be “8B/10B” encoded data, or equivalent. This
parallel data is latched into the input register of the
transmitter section on the rising edge of the reference
clock (used as the transmit byte clock). A 1062.5 MHz
reference clock is used in Fibre Channel operation,
whereas a 125 MHz reference clock is used in Gigabit
Ethernet operation.
The transmitter section’s PLL locks to the user
supplied reference byte clock. This clock is then
multiplied by 10 to generate the high speed serial
clock used to generate the high speed output. The
high speed outputs are capable of inter-facing directly
to copper cables for electrical transmission or to a
separate fiber optic module for optical transmission.
Features
• IEEE 802.3z gigabit ethernet compatible
• ANSI x3.230-1994 fibre channel compatible (FC-O)
• Supports serial data rates of 1062.5 MBd (Fibre
Channel) and 1250 MBd (Gigabit Ethernet)
• Low power consumption, 630 mW typical
• Transmitter and receiver functions incorporated onto a
single IC
• Three package sizes available:
– 10 mm TQFP (HDMP-T1636AG)
– 10 mm PQFP (HDMP-1636AG)
– 10 mm PQFP (HDMP-1646AG)
• 10-bit wide parallel TTL compatible I/Os
• Single +3.3 V power supply
• 5-volt tolerant I/Os
• 2 kV ESD protection o n all pins
Applications
• 1250 MBd Gigabit Ethernet interface
• 1062.5 MBd Fibre Channel interface
• Mass storage system I/O channel
• Work station/server I/O channel
• Backplane serialization
• FC interface for disk drives and arrays
CAUTION:
As with all semiconductor ICs, it is advised that normal static precautions be taken in
handling and assembly of this component to prevent damage and/or degradation which may be
induced by electrostatic discharge (ESD).
HDMP-16x6AG
TRANSMITTER SECTION
SERIAL DATA OUT
PLL
PROTOCOL DEVICE
RBC0
RBC1
PLL
RECEIVER SECTION
SERIAL DATA IN
BYTSYNC
REFCLK
ENBYTSYNC
Figure 1. Typical application using the HDMP-1636AG/1646AG/T1636AG.
INPUT
LATCH
DATA BYTE
TX[0-9]
FRAME
MUX
OUTPUT
SELECT
INTERNAL
LOOPBACK
± DOUT
LOOPEN
TXCAP0
TXCAP1
TX
PLL/CLOCK
GENERATOR
INTERNAL
TX CLOCKS
INPUT
SELECT
± DIN
REFCLK
RXCAP0
RXCAP1
RBC0
RBC1
RX
PLL/CLOCK
RECOVERY
SIGNAL
DETECT
SIG_DET
OUTPUT
DRIVER
DATA BYTE
RX[0-9]
FRAME
DEMUX
AND
BYTE SYNC
INTERNAL
RX CLOCKS
INPUT
SAMPLER
BYTSYNC
ENBYTSYNC
Figure 2. HDMP-1636AG/1646AG/T1636AG transceiver block diagram.
2
The receiver section accepts a
serial electrical data stream at
1062.5 MBd or 1250 MBd and
recovers the original 10-bit wide
parallel data. The receiver PLL
locks onto the incoming serial
signal and recovers the high
speed serial clock and data. The
serial data is converted back
into 10-bit parallel data,
recognizing the 8B/10B comma
character to establish byte
alignment.
The recovered parallel data is
presented to the user at TTL
compatible outputs. The receiver
section also recovers two
receiver byte clocks which are
180 degrees out of phase with
each other. For Gigabit Ethernet,
these clocks are 62.5 MHz,
whereas for Fibre Channel, they
are 53.125 MHz. The parallel
data is properly aligned with the
rising edge of alternating clocks.
For test purposes, the
transceiver provides for on-chip
local loop-back functionality,
controlled through an external
input pin. Additionally, the byte
synchronization feature may be
disabled. This may be useful in
proprietary applications which
use alternative methods to align
the parallel data.
HDMP-1636AG/1646AG/T1636AG
Block Diagram
The HDMP-1636AG/1646AG/
T1636AG was designed to
transmit and receive 10-bit wide
parallel data over a single high-
speed line. The parallel data
applied to the transmitter is
expected to be 8B/10B encoded.
In order to accomplish this task,
the HDMP-1636AG/1646AG/
T1636AG incorporates the
following:
• TTL Parallel I/Os
• High Speed Phase Locked Loops
• Parallel to Serial Converter
• High Speed Serial Clock and
Data Recovery Circuitry
• Comma Character Recognition
Circuitry as per 8B/10B
Specifications
• Byte Alignment Circuitry
• Serial to Parallel Converter
INPUT LATCH
The transmitter accepts 10-bit
wide TTL parallel data at inputs
TX[0..9]. The user-provided
reference clock signal, REFCLK,
is also used as the transmit byte
clock. The TX[0..9] and REFCLK
signals must be properly aligned,
as shown in Figure 3.
TX PLL/CLOCK GENERATOR
The transmitter Phase Locked
Loop and Clock Generator (TX
PLL/CLOCK GENERATOR)
block is responsible for
generating all internal clocks
needed by the transmitter
section to perform its functions.
These clocks are based on the
supplied reference byte clock
(REFCLK). REFCLK is used as
both the frequency reference
clock for the PLL and the
transmit byte clock for the
incoming data latches. It is
expected to be properly aligned
to the incoming parallel data
(see Figure 3). This clock is then
multiplied by 10 to generate the
high speed clock necessary for
clocking the high speed serial
outputs.
FRAME MUX
The FRAME MUX accepts the
10-bit wide parallel data from
the INPUT LATCH. Using
internally generated high speed
clocks, this parallel data is
multiplexed into the high speed
serial data stream. The data bits
are transmitted sequentially,
from the least significant bit
(TX[0]) to the most significant
bit (TX[9]).
OUTPUT SELECT
The OUTPUT SELECT block
provides for an optional internal
loopback of the high speed serial
signal for testing purposes.
In normal operation, LOOPEN is
set low and the serial data
stream is placed at
±DOUT.
When wrap-mode is activated by
setting LOOPEN high, the
±DOUT
pins are held static at
logic 1 and the serial output
signal is internally wrapped to
the INPUT SELECT box of the
receiver section.
INPUT SELECT
The INPUT SELECT block
determines whether the signal at
±DIN
or the internal loop-back
serial signal is used. In normal
operation, LOOPEN is set low
and the serial data is accepted at
±DIN.
When LOOPEN is set high,
the high speed serial signal is
internally looped-back from the
transmitter section to the
receiver section. This feature
allows for loop back testing
exclusive of the transmission
medium.
RX PLL/CLOCK RECOVERY
The RX PLL/CLOCK RECOVERY
block is responsible for
frequency and phase locking
onto the incoming serial data
stream and recovering the bit
and byte clocks. An automatic
locking feature allows the Rx
PLL to lock onto the input data
stream without external PLL
training controls. It does this by
continually frequency locking
onto the reference clock, and
then phase locking onto the
input data stream. An internal
signal detection circuit monitors
the presence of the input, and
invokes the phase detection as
the data stream appears. Once
bit locked, the receiver generates
the high speed sampling clock
3
for the input sampler, and
recovers the two receiver byte
clocks (RBC1/RBC0). These
clocks are 180 degrees out of
phase with each other, and are
alternately used to clock out the
10-bit parallel output data.
INPUT SAMPLER
The INPUT SAMPLER is re-
sponsible for converting the
serial input signal into a retimed
serial bit stream. In order to
accomplish this, it uses the high
speed serial clock recovered
from the RX PLL/CLOCK
RECOVERY block. This serial bit
stream is sent to the FRAME
DEMUX and BYTE SYNC block.
FRAME DEMUX AND BYTE SYNC
The FRAME DEMUX AND BYTE
SYNC block is responsible for
restoring the 10-bit parallel data
from the high speed serial bit
stream. This block is also
responsible for recognizing the
comma character (or a K28.5
character) of positive disparity
(0011111xxx). When recognized,
the FRAME DEMUX AND BYTE
SYNC block works with the RX
PLL/CLOCK RECOVERY block
to properly align the receive byte
clocks to the parallel data. When
a comma character is detected
and realignment of the receiver
byte clocks (RBC1/RBC0) is
necessary, these clocks are
stretched, not slivered, to the
next possible correct alignment
position. These clocks will be
fully aligned by the start of the
second 2-byte ordered set. The
second comma character
received shall be aligned with
the rising edge of RBC1. As per
the 8B/10B encoding scheme,
comma characters must not be
transmitted in consecutive bytes
to allow the receiver byte clocks
to maintain their proper
recovered frequencies.
OUTPUT DRIVERS
The OUTPUT DRIVERS present
the 10-bit parallel recovered
data byte properly aligned to the
receive byte clocks
(RBC1/RBC0), as shown in
Figure 5. These output data
buffers provide TTL compatible
signals.
SIGNAL DETECT
The SIGNAL DETECT block
examines the differential
amplitude of the inputs
±DIN.
When this input signal is too
small, it outputs a logic 0 at
SIG_DET (refer to SIG_DET pin
definition for detection
thresholds), and at the same
time, forces the parallel output
RX[0]..RX[9] to all logic one
(1111111111). The main purpose
of this circuit is to prevent the
generation of random data when
the serial input lines are
disconnected. When the signal at
±DIN
is of a valid amplitude,
SIG_DET is set to logic 1, and
the output of the INPUT SELECT
block is passed through.
HDMP-1636AG/1646AG/T1636AG (Transmitter Section) – Gigabit Ethernet Timing Characteristics
T
A
= 0°C to +70°C, V
CC
= 3.15 V to 3.45 V
Symbol
Parameter
Units
Min.
Typ.
t
setup
Setup Time
nsec
1.5
t
hold
Hold Time
nsec
1.0
t_txlat
[1]
Transmitter Latency
nsec
3.5
bits
4.4
Max.
Note:
1. The transmitter latency, as shown in Figure 4, is defined as the time between the latching in of the parallel data word (as triggered by the rising edge
of the transmit byte clock, REFCLK) and the transmission of the first serial bit of that parallel word (defined by the rising edge of the first bit
transmitted).
4
HDMP-1636AG/1646AG/T1636AG (Transmitter Section) – Fibre Channel Timing Characteristics
T
A[1]
= 0°C to +70°C, V
CC
= 3.15 V to 3.45 V
Symbol
Parameter
Units
Min.
Typ.
t
setup
Setup Time
nsec
2
t
hold
Hold Time
nsec
1.5
t_txlat
[2]
Transmitter Latency
nsec
4.2
bits
4.4
Max.
Notes:
1. Device tested and characterized under T
A
conditions specified, with T
C
monitored at approximately 20° higher than T
A
.
2. The transmitter latency, as shown in Figure 4, is defined as the time between the latching in of the parallel data word (as triggered by the rising edge
of the transmit byte clock, REFCLK) and the transmission of the first serial bit of that parallel word (defined by the rising edge of the first bit
transmitted).
;;;; ;;;;
;; ;;
REFCLK
TX[0]-TX[9]
DATA
DATA
DATA
DATA
DATA
t
SETUP
t
HOLD
1.4 V
2.0 V
0.8 V
Figure 3. Transmitter section timing.
± DOUT
TX[0]-TX[9]
REFCLK
;;; ;;;
;;
;;;
DATA BYTE A
T5
T6
T7
T8
T9
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T0
t_TXLAT
DATA BYTE B
DATA BYTE B
T1
T2
T3
T4
T5
DATA BYTE C
1.4 V
Figure 4. Transmitter latency.
5
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