ACOM to DCOM ...............................................................................
±0.5V
Digital Inputs to Common ............................................. –1V to (V
CC
–0.7V)
External Voltage Applied to BPO and Range Resistors ....................
±V
CC
V
REF OUT
.......................................................... Indefinite Short to Common
V
OUT
............................................................... Indefinite Short to Common
SDO ............................................................... Indefinite Short to Common
Power Dissipation .......................................................................... 750mW
Storage Temperature ...................................................... –60°C to +150°C
Lead Temperature (soldering, 10s) ............................................... +300°C
NOTE: (1) Stresses above those listed under
Absolute Maximum Ratings
may
cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
For the most current package and ordering information, see
the Package Option Addendum at the end of this document,
or see the TI website at www.ti.com.
PIN CONFIGURATION
Top View
CLK
A
0
A
1
SDI
SDO
DCOM
+V
CC
ACOM
1
2
3
4
DAC714
5
6
7
8
12 V
REF OUT
11 R
BPO
10 R
FB2
9
V
OUT
16 CLR
15 –V
CC
14 Gain Adjust
13 Offset Adjust
SO/DIP
PIN DESCRIPTIONS
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
LABEL
CLK
A
0
A
1
SDI
SDO
DCOM
+V
CC
ACOM
V
OUT
R
FB2
R
BPO
V
REF OUT
Offset Adjust
Gain Adjust
–V
CC
CLR
DESCRIPTION
Serial Data Clock
Enable for Input Register (Active Low)
Enable for D/A Latch (Active Low)
Serial Data Input
Serial Data Output
Digital Ground
Positive Power Supply
Analog Ground
D/A Output
±10V
Range Feedback Output
Bipolar Offset
Voltage Reference Output
Offset Adjust
Gain Adjust
Negative Power Supply
Clear
2
DAC714
www.ti.com
SBAS032A
ELECTRICAL CHARACTERISTICS
At T
A
= +25°C, +V
CC
= +12V and +15V, –V
CC
= –12V, and –15V, unless otherwise noted.
DAC714P, U
PARAMETER
TRANSFER CHARACTERISTICS
ACCURACY
Linearity Error
T
MIN
to T
MAX
Differential Linearity Error
T
MIN
to T
MAX
Monotonicity
Monotonicity Over Spec Temp Range
Gain Error
(3)
T
MIN
to T
MAX
Unipolar/Bipolar Zero Error
(3)
T
MIN
to T
MAX
Power Supply Sensitivity of Gain
DYNAMIC PERFORMANCE
Settling Time
(to
±0.003%FSR,
5kΩ || 500pF Load)
(4)
20V Output Step
1LSB Output Step
(5)
Output Slew Rate
Total Harmonic Distortion
0dB, 1001Hz, f
S
= 100kHz
–20dB, 1001Hz, f
S
= 100kHz
–60dB, 1001Hz, f
S
= 100kHz
SINAD: 1001Hz, f
S
= 100kHz
Digital Feedthrough
(5)
Digital-to-Analog Glitch Impulse
(5)
Output Noise Voltage (includes reference)
ANALOG OUTPUT
Output Voltage Range
+V
CC
, –V
CC
=
±11.4V
Output Current
Output Impedance
Short Circuit to ACOM Duration
REFERENCE VOLTAGE
Voltage
T
MIN
to T
MAX
Output Resistance
Source Current
Short Circuit to ACOM Duration
INTERFACE
RESOLUTION
DIGITAL INPUTS
Serial Data Input Code
Logic Levels
(1)
V
IH
V
IL
I
IH
(V
I
= +2.7V)
I
IL
(V
I
= +0.4V)
DIGITAL OUTPUT
Serial Data
V
OL
(I
SINK
= 1.6mA)
V
OH
(I
SOURCE
= 500µA), T
MIN
to T
MAX
POWER SUPPLY REQUIREMENTS
Voltage
+V
CC
–V
CC
Current (No Load,
±15V
Supplies)
(6)
+V
CC
–V
CC
Power Dissipation
(7)
TEMPERATURE RANGES
Specification
All Grades
Storage
Thermal Coefficient,
θ
JA
16
16
16
16
Bits
±4
±8
±4
±8
14
13
±0.1
±0.25
±0.1
±0.2
±0.003
±30
15
14
±0.1
±0.25
±0.1
±0.2
±0.003
±30
±2
±4
±2
±4
16
15
±0.1
±0.25
±0.1
±0.2
±0.003
±30
±1
±2
±1
±2
16
16
±0.1
±0.25
±0.1
±0.2
±0.003
±30
±1
±2
±1
±1
LSB
LSB
LSB
LSB
Bits
Bits
%
%
% of FSR
(2)
% of FSR
%FSR/%V
CC
ppm FSR/%V
CC
MIN
TYP
MAX
MIN
DAC714HB
TYP
MAX
MIN
DAC714HC
TYP
MAX
MIN
DAC714HL
TYP
MAX
UNITS
6
4
10
0.005
0.03
3.0
87
2
15
120
10
6
4
10
0.005
0.03
3.0
87
2
15
120
10
6
4
10
0.005
0.03
3.0
87
2
15
120
10
6
4
10
0.005
0.03
3.0
87
2
15
120
10
µs
µs
V/µs
%
%
%
dB
nV–s
nV–s
nV/√Hz
±10
±5
0.1
Indefinite
+9.975
+9.960
2
Indefinite
+10.000
1
+10.025
+10.040
±10
±5
0.1
Indefinite
+9.975
+9.960
2
Indefinite
+10.000
1
+10.025
+10.040
±10
±5
0.1
Indefinite
+9.975
+9.960
2
Indefinite
+10.000 +10.025
+10.040
1
±10
±5
0.1
Indefinite
+9.975
+9.960
2
Indefinite
+10.000 +10.025
+10.040
1
V
mA
Ω
V
V
Ω
mA
+2.0
0
(V
CC
–1.4)
+0.8
±10
±10
+2.0
0
Binary Two’s Complement
(V
CC
–1.4) +2.0
+0.8
±10
±10
0
(V
CC
–1.4)
+0.8
±10
±10
+2.0
0
(V
CC
–1.4)
+0.8
±10
±10
V
V
µA
µA
0
+2.4
+0.4
+5
0
+2.4
+0.4
+5
0
+2.4
+0.4
+5
0
+2.4
+0.4
+5
V
V
+11.4
–11.4
+15
–15
13
22
+16.5
–16.5
16
26
625
+11.4
–11.4
+15
–15
13
22
+16.5
–16.5
16
26
625
+11.4
–11.4
+15
–15
13
22
+16.5
–16.5
16
26
625
+11.4
–11.4
+15
–15
13
22
+16.5
–16.5
16
26
625
V
V
mA
mA
mW
–40
–60
75
+85
+150
–40
–60
75
+85
+150
–40
–60
75
+85
+150
0
–60
75
+70
+150
°C
°C
°C/W
NOTES: (1) Digital inputs are TTL and +5V CMOS compatible over the specification temperature range. (2) FSR means Full Scale Range. For example, for
±10V
output, FSR = 20V. (3) Errors
externally adjustable to zero. (4) Maximum represents the 3σ limit. Not 100% tested for this parameter. (5) For the worst-case Binary Two’s Complement code changes: FFFF
H
to 0000
H
and 0000
H
to FFFF
H
. (6) During power supply turn on, the transient supply current may approach 3x the maximum quiescent specification. (7) Typical (i.e. rated) supply voltages times maximum currents.
DAC714
SBAS032A
www.ti.com
3
TIMING SPECIFICATIONS
T
A
= –40°C to +85°C, +V
CC
= +12V or +15V, –V
CC
= –12V or –15V.
SYMBOL
t
CLK
t
CL
t
CH
t
A0S
t
A1S
t
AOH
t
A1H
t
DS
t
DH
t
DSOP
t
CP
PARAMETER
Data Clock Period
Clock LOW
Clock HIGH
Setup Time for A
0
Setup Time for A
1
Hold Time for A
0
Hold Time for A
1
Setup Time for DATA
Hold Time for DATA
Output Propagation Delay
Clear Pulsewidth
MIN
100
50
50
50
50
0
0
50
10
140
200
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TRUTH TABLE
A
0
0
1
1
0
X
X
A
1
1
0
1
0
X
X
CLK
1
→
0
→
1
1
→
0
→
1
1
→
0
→
1
1
→
0
→
1
1
X
CLR
1
1
1
1
1
0
DESCRIPTION
Shift Serial Data into SDI
Load D/A Latch
No Change
Two Wire Operation
(1)
No Change
Reset D/A Latch
NOTES: X = Don’t Care. (1) All digital input changes will appear at the
京公网安备 11010802033920号
EEWORLD
