BCY58PSTZ datasheet, PDF - EEWORLD Datasheet

BCY58PSTZ: DescriptionSmall Signal Bipolar Transistor, 0.2A I(C), 32V V(BR)CEO, 1-Element, NPN, Silicon, TO-92 STYLE, E-LINE PACKAGE-3; CategoryDiscrete semiconductor The transistor; File Size32KB，1 Pages; ManufacturerDiodes; Websitehttp://www.diodes.com/

Download Datasheet Parametric View All

BCY58PSTZ Overview

Small Signal Bipolar Transistor, 0.2A I(C), 32V V(BR)CEO, 1-Element, NPN, Silicon, TO-92 STYLE, E-LINE PACKAGE-3

Parameter Name	Attribute value
Maker	Diodes
Parts packaging code	TO-92
package instruction	IN-LINE, R-PSIP-T3
Contacts	3
Reach Compliance Code	unknown
ECCN code	EAR99
Other features	LOW NOISE
Maximum collector current (IC)	0.2 A
Collector-emitter maximum voltage	32 V
Configuration	SINGLE
Minimum DC current gain (hFE)	120
JESD-30 code	R-PSIP-T3
JESD-609 code	e3
Humidity sensitivity level	1
Number of components	1
Number of terminals	3
Package body material	PLASTIC/EPOXY
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	260
Polarity/channel type	NPN
Certification status	Not Qualified
Guideline	CECC
surface mount	NO
Terminal surface	MATTE TIN
Terminal form	THROUGH-HOLE
Terminal location	SINGLE
Maximum time at peak reflow temperature	40
transistor applications	SWITCHING
Transistor component materials	SILICON
Nominal transition frequency (fT)	125 MHz
Maximum off time (toff)	800 ns
Maximum opening time (tons)	150 ns

As the Spring Festival holiday approaches, the forum has quietly launched a new feature (or a new page?) Let's see who discovers it first: The key points are all in the title~ Come and reply to see who has found it? ?...; okhxyyo Talking

Why can't the wireless network card get all the data?: It's the ndisprot example that comes with DDK. I bind a wired network card and install ndisprot drivers on both machines. One sends, one receives, (wired to wired) everything is OK. I send a packet fi...; moto_jfx Embedded System

FPGA implementation of sliding average filtering algorithm and LZW compression algorithm.pdf: FPGA implementation of sliding average filtering algorithm and LZW compression algorithm.pdf...; zxopenljx FPGA/CPLD

Several commonly used anti-reverse connection protection circuits: [i=s]This post was last edited by Baboerben on 2020-4-24 20:38[/i]1. Usually, the DC power input reverse connection protection circuit uses the unidirectional conductivity of the diode to achieve reve...; 灞波儿奔 Analogue and Mixed Signal

The following error message appears during compilation. What is this error? Thank you.: When compiling the Verilog program, the following error occurs. What is this error? ? ? Thank you. My project is placed in the English directory....; 江汉大学南瓜 FPGA/CPLD

Could you please tell me what the % ! etc. in the function mean?: What do the % ! and so on in the function mean? This function can be passed by the Diab compiler, but not by the Green Hills Multi compiler. It should be a PowerPC instruction or an assembly instructi...; xiaoshahai9 Embedded System

Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

Popular Components