T80C5112
8-bit Microcontroller with A/D converter
1. Description
The T80C5112 is a high performance ROM/OTP version
of the 80C51 8-bit microcontroller.
The T80C5112 retains all the features of the standard
80C51 with 8 Kbytes ROM/OTP program memory, 256
bytes of internal RAM, a 8-source , 4-level interrupt
system, an on-chip oscillator and two timer/counters.
The T80C5112 is dedicated for analog interfacing
applications. For this, it has an 10-bit, 8 channels A/D
converter and a five channels Programmable Counter
Array.
In addition, the T80C5112 has a Hardware Watchdog
Timer with its own low power oscillator, a versatile
serial
channel
that
facilitates
multiprocessor
communication (EUART) with an independent baud rate
generator, a SPI serial bus controller and a X2 speed
improvement mechanism. The X2 feature allows to keep
the same CPU power at a divided by two oscillator
frequency.
The fully static design of the T80C5112 allows to reduce
system power consumption by bringing the clock
frequency down to any value, even DC, without loss of
data.
The T80C5112 has 3 software-selectable modes of
reduced activity for further reduction in power
consumption. In the idle mode the CPU is frozen while
the peripherals are still operating. In the quiet mode, the
A/D converter only is operating. In the power-down
mode the RAM is saved and all other functions are
inoperative. Two oscillators source, crystal and RC,
provide a versatile power management.
The T80C5112 is proposed in 48/52 pin count packages
with Port 0 and Port 2 (address / data busses).
2. Features
·
·
80C51 Compatible
Five I/O ports
·
Two 16-bit timer/counters
·
256 bytes RAM
8Kbytes ROM/OTP program memory with 64 bytes
encryption array and 3 security levels.
Crystal or ceramic oscillator with hardware set
up (32 KHz or 33/40 MHz)
·
Internal RC oscillator (12 MHz)
·
Programmable prescaler
·
Active oscillator during reset defined by hardware
set up
·
Timer 0 subclock mode for Real Time Clock.
Programmable counter array with High speed output,
Compare / Capture, Pulse Width Modulation and
Watchdog timer capabilities
·
·
·
·
High-Speed Architecture
33MHz @ 5V (66 MHz equivalent)
·
20MHz @ 3V (40 MHz equivalent)
·
X2 Speed Improvement capability (6 clocks/
machine cycle)
10-bit, 8 channels A/D converter
·
·
·
Interrupt Structure with:
8 Interrupt sources,
·
4 interrupt priority levels
Power Control modes:
·
·
·
·
·
·
·
Hardware Watchdog Timer with integrated low
power oscillator (20m A) and Reset-Out
·
·
Programmable I/O mode: standard C51, input only,
push-pull, open drain.
Asynchronous port reset, Power On Reset
Full duplex Enhanced UART with baud rate generator
SPI, master/slave mode
Dual system clock
·
·
·
Idle mode
·
Power-down mode
·
Power-off Flag, Power fail detect, Power on Reset
Power supply: 2.7 to 5.5V
Temperature ranges: Commercial (0 to 70C) and
Industrial (-40 to 85 C), optionnal extented
Package:LQFP48 (body 7*7*1.4mm), PLCC52
Rev. B - November 10, 2000
1
Preliminary
T80C5112
3. Block Diagram
CEX0-4
ECI
MISO
MOSI
SPSCK
SS
(3) (3) (3) (3)
RxD
TxD
Vcc
Vss
(2) (2)
(2)
XTAL1
(2)
XTAL2
Xtal
Osc
(1) (1)
EUART
BRG
RAM
256
x8
ROM /OTP
PCA
SPI
8 K *8
Watch
Dog
RC
Osc
C51
CORE
RC
Osc
IB-bus
CPU
RST
EA
ALE
PSEN
Timer 0
Timer 1
INT
Ctrl
Vref
generator
A/D
Converter
Parallel I/O Ports
Port 1 Port 3 Port 4
Port 0
Port 2
INT1
INT0
AIN0-7
(2)
Vpp
(2) (3)
T0
T1
(2) (3)
Vref
(3)
P1
P3
P4
P0
P2
(1): Alternate function of Port 1
(2): Alternate function of Port 3
(3): Alternate function of Port 4
2
Rev. B - November 10, 2000
Preliminary
T80C5112
4. alias SFR Mapping
The Special Function Registers (SFRs) of the T80C5112 belongs to the following categories:
·
·
·
·
·
·
·
·
·
·
C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR, AUXR1
I/O port registers: P0, P1, P2, P3, P4, P1M1, P1M2, P3M1, P3M2, P4M1, P4M2
Timer registers: TCON, TH0, TH1, TMOD, TL0, TL1
Serial I/O port registers: SADDR, SADEN, SBUF, SCON, BRL, BDRCON
Power and clock control registers: CKCON0, CKCON1, OSCCON, CKSEL, PCON, CKRL
Interrupt system registers: IE, IE1, IPL0, IPL1, IPH0, IPH1
WatchDog Timer: WDTRST, WDTPRG
SPI: SPCON, SPSTA, SPDAT
PCA: CCAP0L, CCAP1L, CCAP2L, CCAP3L, CCAP4L, CCAP0H, CCAP1H, CCAP2H, CCAP3H,
CCAP4H, CCAPM0, CCAPM1, CCAPM2, CCAPM3, CCAPM4, CL, CH, CMOD, CCON
ADC: ADCCON, ADCCLK, ADCDATH, ADCDATL, ADCF
Table 1. SFR Addresses and Reset Values
0/8
F8h
F0h
E8h
E0h
D8h
D0h
C8h
C0h
B8h
B0h
A8h
A0h
98h
90h
88h
80h
P4
1111 1111
IPL0
0000 0000
P3
1111 1111
IE0
0000 0000
P2
1111 1111
SCON
0000 0000
P1
1111 1111
TCON
0000 0000
P0
1111 1111
0/8
TMOD
0000 0000
SP
0000 0111
1/9
TL0
0000 0000
DPL
0000 0000
2/A
TL1
0000 0000
DPH
0000 0000
3/B
4/C
TH0
0000 0000
TH1
0000 0000
AUXR
XXXXXXX0
SBUF
XXXX XXXX
SADEN
0000 0000
IE1
0000 0000
SADDR
0000 0000
AUXR1
XXXXXXX0
BRL
0000 0000
BDRCON
0000 0000
CKRL
1111 1111
CKCON0
X000X000
PCON
00X1 0000
7/F
WDRST
0000 0000
IPL1
0000 0000
IPH1
0000 0000
IPH0
X000 0000
SPCON
0001 0100
SPSTA
SPDAT
XXXXXXXX XXXX XXXX
ACC
0000 0000
CCON
00X0 0000
PSW
0000 0000
CMOD
X000 0000
B
0000 0000
CL
0000 0000
1/9
CH
0000 0000
2/A
3/B
4/C
5/D
6/E
7/F
FFh
F7h
CONF
1111 111X
EFh
E7h
CCAPM4
X000 0000
P4M1
0000 0000
DFh
D7h
CFh
C7h
BFh
B7h
CCAP0H
CCAP1H
CCAP2H
CCAP3H
CCAP4H
XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
ADCLK
0000 0000
ADCON
0000 0000
ADDL
XXXXXX00
ADDH
0000 0000
ADCF
0000 0000
CCAP0L
CCAP1L
CCAP2L
CCAP3L
CCAP4L
XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
P1M2
0000 0000
CCAPM0
00XX X000
CCAPM1
X000 0000
P3M2
0000 0000
CCAPM2
X000 0000
P1M1
0000 0000
P4M2
0000 0000
CCAPM3
X000 0000
P3M1
0000 0000
CKCON1
AFh
XXXX XXX0
WDTPRG
0000 0000
A7h
9Fh
97h
8Fh
87h
CKSEL
OSCCON
XXXX XXXC XXXX XXCC
5/D
6/E
Notes:
"C", value defined by the configuration byte, see Section ÒConfiguration byteÓ, page 11
Rev. B - November 10, 2000
3
Preliminary
T80C5112
5. Pin Configuration
P4.6/AIN6/SPSCK
P4.4/AIN4/MISO
P4.5/AIN5/MOSI
P4.3/AIN3/INT1
P4.2/AIN2/SS
P4.1/AIN1/T1
P4.7/AIN7
P1.0/WR
RST
48 47 46 45 44 43 42 41 40 39 38 37
VREF
VSS + AVSS
P2.7
P2.6
P2.5
P2.4
P2.3
V2.2
VCC + AVCC
P2.1
P2.0
P3.7
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
P3.0/RxD
P3.1/TxD
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P1.2/ECI
P1.3/CEX0
EA
P1.1/RD
P4.0/AIN0
LQFP48
7*7*1.4 mm
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
XTAL1/P3.4
P1.7/CEX4
P1.6/CEX3
ALE
P3.2/INT0
P1.5/CEX2
XTAL2/P3.5
P4.6/AIN6/SPSCK
P4.5/AIN5/MOSI
P4.4/AIN4/MISO
P4.3/AIN3/INT1
P4.2/AIN2/SS
P1.4/CEX1
P3.3/T0
PSEN
VPP
P3.6
P4.1/AIN1/T1
P4.7/AIN7
7 6 5 4 3 2 1 52 51 50 49 48 47
VSS
AVSS
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
AVCC + VCC
P2.1
P2.0
P3.7
VPP
P4.0/AIN0
P1.0/WR
P1.1/RD
VREF
RST
EA
8
9
10
11
12
13
14
15
16
17
18
19
20
21 22 23 24 25 26 27 28 29 30 31 32 33
P3.4
P1.7/CEX4
P1.6/CEX3
ALE
P3.2/INT0
P1.5/CEX2
P1.4/CEX1
P3.3/T0
P3.6
P3.5
XTAL2
XTAL1
PSEN
46
45
44
43
42
41
40
39
38
37
36
35
34
NIC
P3.0/RxD
P3.1/TxD
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P1.2/ECI
P1.3/CEX0
PLCC52
*NIC: No Internal Connection
4
Rev. B - November 10, 2000
Preliminary
T80C5112
PIN
NUMBER
MNEMONIC LQFP
48
V
SS
V
CC
AV
SS
AV
CC
VREF
VPP
X
X
X
X
X
X
TYPE
NAME AND FUNCTION
PLCC
52
X
X
X
I
I
I
I
I
I
I/O
Ground:
0V reference.
Power Supply:
This is the power supply voltage for normal, idle and power-
down operation.
Analog Ground:
0V reference.
Analog Power Supply:
This is the power supply voltage for normal and idle
operation of the A/D
VREF :
A/D converter positive reference input.
Vpp :
Programming Supply Voltage:
This pin also receives the 12V programming pulse which will start the EPROM
programming and the manufacturer test modes.
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins
that have 1s written to them are pulled high by the internal pull-ups and can be
used as inputs.
Alternate functions for Port 1 include:
WR (P1.0):
External data memory write strobe
RD (P1.1):
External data memory readstrobe
ECI (P1.2):
External Clock for the PCA
CEX0 (P1.3):
Capture/Compare External I/O for PCA module 0
CEX1 (P1.4):
Capture/Compare External I/O for PCA module 1
CEX2 (P1.5):
Capture/Compare External I/O for PCA module 2
CEX3 (P1.6):
Capture/Compare External I/O for PCA module 3
CEX4 (P1.7):
Capture/Compare External I/O for PCA module 4
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins
that have 1s written to them are pulled high by the internal pull-ups and can be
used as inputs.
P3.4 and P3.5 are valid I/O pins only when the T80C5112 is using the internal
RC oscillator, OSCB.
P3.6 is an input only pin
Port 3 also serves the special features of the 80C51 family, as listed below.
RXD (P3.0):
Serial input port
TXD (P3.1):
Serial output port
INT0 (P3.2):
External interrupt 0
T0 (P3.3):
Timer 0 external input
XTAL1 (P3.4):
Input to the inverting oscillator amplifier and input to the internal
clock generator circuits, selected by hardware set up
a
XTAL2 (P3.5):
Output from the inverting oscillator amplifier, selected by
hardware set up
Port 4:
Port 4 is an 8-bit bidirectional I/O port. Each bit can be set as pure
CMOS input or as push-pull output.
Port 4 is also the input port of the Analog to digital converter and used for
oscillator and reset.
AIN0 (P4.0):
A/D converter input 0
AIN1 (P4.1):
A/D converter input 1
T1:
Timer 1 external input
AIN2 (P4.2):
A/D converter input 2
SS:
Slave select input of the SPI controller
P1.0-P1.7
X
X
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P3.0-P3.7
X
X
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P4.0-P4.7
X
X
I/O
I/O
I/O
I/O
Rev. B - November 10, 2000
5
Preliminary
Power technology
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