CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
DC Supply Voltage
DC Supply Current (Low State)
(Note 2)
Threshold Voltage
Trigger Voltage
T
A
= 25
o
C, V+ = 5V to 15V Unless Otherwise Specified
CA555
SYMBOL
V+
I+
V+ = 5V, R
L
=
∞
V+ = 15V, R
L
=
∞
V
TH
V+ = 5V
V+ = 15V
TEST CONDITIONS
MIN
4.5
-
-
-
1.45
4.8
-
I
TH
-
0.4
-
V+ = 5V
V+ = 15V
2.9
9.6
-
-
-
-
-
-
3.0
13.0
-
-
-
-
t
R
t
F
-
-
TYP
-
3
10
(
2
/
3
)V+
1.67
5
0.5
0.1
0.7
0.1
3.33
10
-
0.1
0.1
0.4
2.0
2.5
3.3
13.3
12.5
0.5
30
0.05
100
100
MAX
18
5
12
-
1.9
5.2
-
0.25
1.0
-
3.8
10.4
-
0.25
0.15
0.5
2.2
-
-
-
-
2
100
0.2
-
-
CA555C, LM555C
MIN
4.5
-
-
-
-
-
-
-
0.4
-
2.6
9
-
-
-
-
-
-
2.75
12.75
-
-
-
-
-
-
TYP
-
3
10
(
2
/
3
)V+
1.67
5
0.5
0.1
0.7
0.1
3.33
10
0.25
-
0.1
0.4
2.0
2.5
3.3
13.3
12.5
1
50
0.1
100
100
MAX
16
6
15
-
-
-
-
0.25
1.0
-
4
11
0.35
-
0.25
0.75
2.5
-
-
-
-
-
-
-
-
-
UNITS
V
mA
mA
V
V
V
µA
µA
V
mA
V
V
V
V
V
V
V
V
V
V
V
%
ppm/
o
C
%/V
ns
ns
Trigger Current
Threshold Current (Note 3)
Reset Voltage
Reset Current
Control Voltage Level
Output Voltage
Low State
V
OL
V+ = 5V, I
SINK
= 5mA
I
SINK
= 8mA
V+ = 15V, I
SINK
= 10mA
I
SINK
= 50mA
I
SINK
= 100mA
I
SINK
= 200mA
Output Voltage
High State
V
OH
V+ = 5V, I
SOURCE
= 100mA
V+ = 15V, I
SOURCE
= 100mA
I
SOURCE
= 200mA
Timing Error (Monostable)
Frequency Drift with Temperature
Drift with Supply Voltage
Output Rise Time
Output Fall Time
NOTES:
R
1
, R
2
= 1kΩ to 100kΩ,
C = 0.1µF
Tested at V+ = 5V, V+ = 15V
2. When the output is in a high state, the DC supply current is typically 1mA less than the low state value.
3. The threshold current will determine the sum of the values of R
1
and R
2
to be used in Figure 4 (astable operation); the maximum total
R
1
+ R
2
= 20MΩ.
2
CA555, CA555C, LM555C
Schematic Diagram
V+
8
4.7K
830
D
1
4.7K
D
2
Q
10
Q
3
Q
4
1K
5K
6.8K
THRESHOLD
COMPARATOR
TRIGGER
COMPARATOR
FLIP-FLOP
OUTPUT
Q
16
Q
19
Q
20
3.9K
OUTPUT
3
THRESHOLD
6
Q
1
Q
2
Q
5
5K
10K
CONTROL
VOLTAGE
5
2
TRIGGER
RESET
4
RESET
7
DISCHARGE
1
V-
Q
6
DISCHARGE
100
Q
8
100K
Q
9
Q
11
Q
12
Q
13
5K
Q
14
Q
7
4.7K
7K
D
3
D
4
Q
18
220
Q
17
Q
15
4.7K
Q
21
NOTE: Resistance values are in ohms.
Typical Applications
Reset Timer (Monostable Operation)
Figure 1 shows the CA555 connected as a reset timer. In this
mode of operation capacitor C
T
is initially held discharged by
a transistor on the integrated circuit. Upon closing the “start”
switch, or applying a negative trigger pulse to terminal 2, the
integral timer flip-flop is “set” and releases the short circuit
across C
T
which drives the output voltage “high” (relay
energized). The action allows the voltage across the capacitor
to increase exponentially with the constant t = R
1
C
T
. When
the voltage across the capacitor equals 2/3 V+, the
comparator resets the flip-flop which in turn discharges the
capacitor rapidly and drives the output to its low state.
Since the charge rate and threshold level of the comparator
are both directly proportional to V+, the timing interval is
relatively independent of supply voltage variations. Typically,
the timing varies only 0.05% for a 1V change in V+.
Applying a negative pulse simultaneously to the reset
terminal (4) and the trigger terminal (2) during the timing
cycle discharges C
T
and causes the timing cycle to restart.
Momentarily closing only the reset switch during the timing
interval discharges C
T
, but the timing cycle does not restart.
R
1
7
CA555
6
1
2
C
T
4.7K
0.01µF
S
1
START
5
10K
RELAY
COIL
RESET
680
4
8
EO
3
1N4001
V+
5V
680
NOTE: All resistance values are in ohms.
FIGURE 1. RESET TIMER (MONOSTABLE OPERATION)
3
CA555, CA555C, LM555C
Figure 2 shows the typical waveforms generated during this
mode of operation, and Figure 3 gives the family of time
delay curves with variations in R
1
and C
T
.
SWITCH S
1
“OPEN”
3V
INPUT
VOLTAGE (TERMINAL 2)
SWITCH S
1
“CLOSED”
0
3.3V
CAPACITOR
VOLTAGE (TERMINALS 6, 7)
0
t
D
5V
OUTPUT
VOLTAGE
(TERMINAL 3)
0
C
T
Repeat Cycle Timer (Astable Operation)
Figure 4 shows the CA555 connected as a repeat cycle
timer. In this mode of operation, the total period is a function
of both R
1
and R
2.
V+
5V
R
1
7
R
2
6
1
2
CA555
5
4
8
EO
3
RELAY
COIL
0.01µF
FIGURE 4. REPEAT CYCLE TIMER (ASTABLE OPERATION)
FIGURE 2. TYPICAL WAVEFORMS FOR RESET TIMER
T = 0.693 (R
1
+ 2R
2
) C
T
= t
1
+ t
2
100
T
A
= 25
o
C
V+ = 5V
where t
1
= 0.693 (R
1
+ R
2
) C
T
and t
2
= 0.693 (R
2
) C
T
the duty cycle is:
R
1
= 1kΩ
10kΩ
100kΩ
1MΩ
10MΩ
10
CAPACITANCE (µF)
1
t
1
R
1
+
R
2
---------------
=
-----------------------
-
-
t
1
+
t
2
R
1
+
2R
2
0.1
0.01
0.001
10
-5
Typical waveforms generated during this mode of operation
are shown in Figure 5. Figure 6 gives the family of curves of
free running frequency with variations in the value of
(R
1
+ 2R
2
) and C
T
.
1
10
10
-4
10
-3
10
-2
TIME DELAY(s)
10
-1
FIGURE 3. TIME DELAY vs RESISTANCE AND CAPACITANCE
4
CA555, CA555C, LM555C
t
1
5V
10
CAPACITANCE (µF)
R
1
+ 2R
2
= 1kΩ
1
100kΩ
1MΩ
0.1
10MΩ
10kΩ
t
2
100
T
A
= 25
o
C, V+ = 5V
0
3.3V
0.01
1.7V
0.001
10
-1
1
10
10
2
10
3
10
4
10
5
0
FREQUENCY (Hz)
Top Trace: Output voltage (2V/Div. and 0.5ms/Div.)
Bottom Trace: Capacitor voltage (1V/Div. and 0.5ms/Div.)
FIGURE 5. TYPICAL WAVEFORMS FOR REPEAT CYCLE TIMER
FIGURE 6. FREE RUNNING FREQUENCY OF REPEAT CYCLE
TIMER WITH VARIATION IN CAPACITANCE AND
RESISTANCE
Typical Performance Curves
MINIMUM PULSE WIDTH (ns)
150
10
T
A
= -55
o
C
0
o
C
25
o
C
50
125
o
C
70
o
C
SUPPLY CURRENT (mA)
9
8
7
6
5
4
3
2
1
0
0.1
0.2
0.3
0.4
0
2.5
5
7.5
10
12.5
15
SUPPLY VOLTAGE (V)
MINIMUM TRIGGER (PULSE) VOLTAGE (x V+) (NOTE)
50
o
C
25
o
C
T
A
= 125
o
C
100
NOTE: Where x is the decimal multiplier of the supply voltage.
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