The LM3146 consists of five high voltage general purpose
silicon NPN transistors on a common monolithic substrate
Two of the transistors are internally connected to form a
differentially-connected pair The transistors are well suited
to a wide variety of applications in low power system in the
dc through VHF range They may be used as discrete tran-
sistors in conventional circuits however in addition they
provide the very significant inherent integrated circuit ad-
vantages of close electrical and thermal matching The
LM3146 is supplied in a 14-lead molded dual-in-line pack-
age for applications requiring only a limited temperature
range
Features
Y
Y
Y
Y
Y
High voltage matched pairs of transistors V
BE
matched
g
5 mV input offset current 2
mA
max at I
C
e
1 mA
Five general purpose monolithic transistors
Operation from dc to 120 MHz
Wide operating current range
Low noise figure
3 2 dB typ at 1 kHz
Applications
Y
Y
Y
General use in all types of signal processing systems
operating anywhere in the frequency range from dc to
VHF
Custom designed differential amplifiers
Temperature compensated amplifiers
Connection Diagram
Dual-In-Line and Small Outline Packages
TL H 7959 – 1
Top View
Order Number LM3146M or LM3146N
See NS Package Number M14A or N14A
C
1995 National Semiconductor Corporation
TL H 7959
RRD-B30M115 Printed in U S A
Absolute Maximum Ratings
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
LM3146
Units
Power Dissipation Each transistor
T
A
e
25 C to 55 C
300
mW
T
A
l
55 C
Derate at 6 67 mW C
Power Dissipation Total Package
T
A
e
25 C
500
mW
T
A
l
25 C
Derate at 6 67 mW C
Collector to Emitter Voltage V
CEO
30
V
40
V
Collector to Base Voltage V
CBO
Collector to Substrate Voltage
V
CIO
(Note 1)
40
V
Emitter to Base Voltage V
EBO
(Note 2)
5
V
Collector to Current I
C
50
mA
b
40 to
a
85
C
Operating Temperature Range
b
65 to
a
150
Storage Temperature Range
C
Soldering Information
Dual-In-Line Package
Soldering (10 seconds)
Small Outline Package
Vapor Phase (60 seconds)
Infrared (15 seconds)
260 C
215 C
220 C
See AN-450 ‘‘Surface Mounting Methods and Their Effect
on Product Reliability’’ for other methods of soldering sur-
face mount devices
DC Electrical Characteristics
T
A
e
25 C
Symbol
V
(BR)CBO
V
(BR)CEO
V
(BR)CIO
V
(BR)EBO
I
CBO
I
CEO
h
FE
Parameter
Collector to Base Breakdown Voltage
Collector to Emitter Breakdown Voltage
Collector to Substrate Breakdown
Voltage
Emitter to Base Breakdown Voltage
(Note 2)
Collector Cutoff Current
Collector Cutoff Current
Static Forward Current Transfer
Ratio (Static Beta)
Input Offset Current for Matched
Pair Q1 and Q2
Base to Emitter Voltage
Magnitude of Input Offset Voltage
for Differential Pair
Temperature Coefficient of Base
to Emitter Voltage
Collector to Emitter Saturation
Voltage
Temperature Coefficient of Input
Offset Voltage
Conditions
Min
I
C
e
10
mA
I
E
e
0
I
C
e
1 mA I
B
e
0
I
CI
e
10
mA
I
B
e
0
I
E
e
0
I
C
e
0 I
E
e
10
mA
V
CB
e
10V I
E
e
0
V
CE
e
10V I
B
e
0
I
C
e
10 mA V
CE
e
5V
I
C
e
1 mA V
CE
e
5V
I
C
e
10
mA
V
CE
e
5V
I
C1
e
1
C2
e
1 mA
V
CE
e
5V
I
C
e
1 mA V
CE
e
3V
V
CE
e
5V I
E
e
1 mA
V
CE
e
5V I
E
e
1 mA
I
C
e
10 mA I
B
e
1 mA
I
C
e
1 mA V
CE
e
5V
0 63
30
40
30
40
5
Limits
Typ
72
56
72
7
0 002
(Note 3)
85
100
90
03
0 73
0 48
b
1 9
Units
Max
V
V
V
V
100
5
nA
mA
I
B1
–I
B2
V
BE
V
BE1
– V
BE2
DV
BE
DT
V
CE(SAT)
DV
10
DT
2
0 83
5
mA
V
mV
mV C
V
mV
C
0 33
11
Note 1
The collector of each transistor is isolated from the substrate by an integral diode The substrate must be connected to a voltage which is more negative
than any collector voltage in order to maintain isolation between transistors and provide normal transistor action To avoid undesired coupling between transistors
the substrate terminal should be maintained at either dc or signal (ac) ground A suitable bypass capacitor can be used to establish a signal ground
Note 2
If the transistors are forced into zener breakdown (V
(BR)EBO
) degradation of forward transfer current ratio (h
FE
) can occur
Note 3
See curve
2
AC Electrical Characteristics
Symbol
NF
f
T
C
EB
C
CB
C
CI
Parameter
Low Frequency Noise Figure
Gain Bandwidth Product
Emitter to Base Capacitance
Collector to Base Capacitance
Collector to Substrate Capacitance
Conditions
Min
f
e
1 kHz V
CE
e
5V
I
C
e
100
mA
R
S
e
1 kX
V
CE
e
5V I
C
e
3 mA
V
EB
e
5V I
E
e
0
V
CB
e
5V I
C
e
0
V
CI
e
5V I
C
e
0
300
Limits
Typ
3 25
500
0 70
0 37
22
Max
dB
MHz
pF
pF
pF
Units
Low Frequency Small Signal Equivalent Circuit Characteristics
h
fe
h
ie
h
oe
h
re
Forward Current Transfer Ratio
Short Circuit Input Impedance
Open Circuit Output Impedance
Open Circuit Reverse Voltage
Transfer Ratio
f
e
1 kHz V
CE
e
3V I
C
e
1 mA
f
e
1 kHz V
CE
e
3V I
C
e
1 mA
f
e
1 kHz V
CE
e
3V I
C
e
1 mA
f
e
1 kHz V
CE
e
3V
I
C
e
1 mA
100
35
15 6
1 8 x 10
b
4
kX
mmho
Admittance Characteristics
Y
fe
Y
ie
Y
oe
Y
re
Forward Transfer Admittance
Input Admittance
Output Admittance
Reverse Transfer Admittance
f
e
1 MHz V
CE
e
3V I
C
e
1 mA
f
e
1 MHz V
CE
e
3V I
C
e
1 mA
f
e
1 MHz V
CE
e
3V I
C
e
1 mA
f
e
1 MHz V
CE
e
3V I
C
e
1 mA
31
b
j 1 5
0 3
a
j 0 04
0 001
a
j 0 03
(Note 3)
mmho
mmho
mmho
mmho
Note 1
The collector of each transistor is isolated from the substrate by an integral diode The substrate must be connected to a voltage which is more negative
than any collector voltage in order to maintain isolation between transistors and provide normal transistor action To avoid undesired coupling between transistors
the substrate terminal should be maintained at either dc or signal (ac) ground A suitable bypass capacitor can be used to establish a signal ground
Note 2
If the transistors are forced into zener breakdown (V
(BR)EBO
) degradation of forward transfer current ratio (h
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