CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T
J
= T
C
= T
A
DC Electrical Specifications
PARAMETER
V
SUPPLY
I
S
V
OS
I
IN
Z
IN
V
DIFF
A
VOL
V
OUT
(200)
V
OUT
(100)
V
N
V
REFOS
PSRR
I
OUT
(min)
R
OUT
V
CC
= +5V, V
EE
= -5V, T
A
= 25°C, V
IN
= 0V, R
L
= 200, unless otherwise specified.
DESCRIPTION
MIN
±3.0
TYP
±5.0
11
-25
-20
10
6
400
±2.0
±2.3
75
±3.4
±2.9
±3.6
±3.1
36
-60
60
50
-25
70
60
0.1
+60
MAX
±6.3
14
40
20
UNITS
V
mA
mV
A
k
V
dB
V
V
nV/Hz
mV
dB
mA
Supply Operating Range (V
CC
–V
EE
)
Power Supply Current (No Load)
Input Referred Offset Voltage
Input Bias Current (V
IN
, V
INB
, V
REF
)
Differential Input Impedance
Differential Input Range
Open Loop Voltage Gain
Output Voltage Swing (200 load, V
OUT
to V
OUTB
)
Output Voltage Swing (100 Load, V
OUT
to V
OUTB
)
Input Referred Voltage Noise
Output Offset Relative to V
REF
Power Supply Rejection Ratio
Minimum Output Current
(V
OUT
= V
OUTB
= 0V) Output Impedance
AC Electrical Specifications
PARAMETER
BW(-3dB)
SR
Tstl
GBW
V
REFBW
(-3dB)
V
REFSR
THDf1
dP
dG
NOTE:
V
CC
= +5V, V
EE
= -5V, T
A
= 25°C, V
IN
= 0V, R
LOAD
= 200, unless otherwise specified
DESCRIPTION
MIN
TYP
150
800
15
400
130
100
-75
0.16
0.24
MAX
UNITS
MHz
V/s
ns
MHz
MHz
V/s
dB
°
%
-3dB Bandwidth (@ gain of 2)
Differential Slewrate
Settling Time to 1%
Gain Bandwidth Product
V
REF
-3dB Bandwidth
V
REF
Slewrate
Distortion at 100kHz (Note 1)
Differential Phase @ 3.58MHz
Differential Gain @ 3.58MHz
1. Distortion measurement quoted for V
OUT
–V
OUTB
= 12V pk-pk, R
LOAD
= 200, V
GAIN
= 8
FN7048 Rev 1.00
February 11, 2005
Page 2 of 6
EL2141
Pin Descriptions
EL2141
2
1
4
3
5
6
7
8
PIN NAME
V
IN
FBP
FBN
V
REF
V
OUTB
V
CC
V
EE
V
OUT
Non-inverting Input
Non-inverting Feedback Input. Resistor R1 must be Connected from this Pin to V
OUT
.
Inverting Feedback Input. Resistor R3 must be Connected from this pin to V
OUTB
.
Output Common-mode Control. The Common-mode Voltage of V
OUT
and V
OUTB
will Follow the Voltage on this Pin.
Note that on the EL2141, this pin is also the V
INB
pin.
Inverting Output
Positive Supply
Negative Supply
Non-inverting Output
FUNCTION
Typical Performance Curves
FIGURE 1. I
S
vs SUPPLY VOLTAGE
FIGURE 2. FREQUENCY RESPONSE vs RESISTOR R2
(GAIN = 2)
FIGURE 3. FREQUENCY RESPONSE vs TEMPERATURE
FIGURE 4. FREQUENCY RESPONSE vs RESISTOR R2
(GAIN = 8)
FN7048 Rev 1.00
February 11, 2005
Page 3 of 6
EL2141
Typical Performance Curves
(Continued)
FIGURE 5. DISTORTION vs FREQUENCY
(GAIN = 6, R
LOAD
= 200) V
IN
= 2V
PK-PK
FIGURE 6. OUTPUT SIGNAL AND COMMON MODE SIGNAL
vs FREQUENCY
Applications Information
The amount of capacitance tolerated on any of these nodes
in an actual application will also be dependent on the gain
setting and the resistor values in the feedback network.
Distortion Considerations
The harmonics that these amplifiers will potentially produce
are the 2nd, 3rd, 5th, and 6th. Their amplitude is application
dependent. All other harmonics should be negligible by com-
parison. Each should be considered separately:
H2
The second harmonic arises from the input stage, and
the lower the applied differential signal amplitude, the lower
the magnitude of the second harmonic. For practical consid-
erations of required output signal and input noise levels, the
user will end up choosing a circuit gain. Referring to Figure 1,
it is best if the voltage at the negative feedback node tracks
the V
REF
node, and the voltage at the positive feedback
node tracks the V
IN
node respectively. This would theoreti-
cally require that R1 + R2 = R3, although the lowest
distortion is found at about R3 = R1 + (0.7*R2). With this
arrangement, the second harmonic should be suppressed
well below the value of the third harmonic.
H3
The third harmonic should be the dominant harmonic and
is primarily affected by output load current which, of course,
is unavoidable. However, this should encourage the user not
to waste current in the gain setting resistors, and to use val-
ues that consume only a small proportion of the load current,
so long as peaking does not occur. The more load current,
the worse the distortion, but depending on the frequency, it
may be possible to reduce the amplifier gain so that there is
more internal gain left to cancel out any distortion.
H5
The fifth harmonic should always be below the third, and
will not become significant until heavy load currents are
drawn. Generally, it should respond to the same efforts
applied to reducing the third harmonic.
H6
The sixth harmonic should not be a problem and is the
result of poor power supply decoupling. While 100nF chip
capacitors may be sufficient for some applications, it would
be insufficient for driving full signal swings into a twisted pair
line at 100kHz. Under these conditions, the addition of 4.7F
tantalum capacitors would cure the problem.
R1
+
R2
+
R3
GAIN
= ------------------------------------
-
R2
Choice of Feedback Resistor
There is little to be gained from choosing resistor R2 values
below 400
and, in fact, it would only result in increased
power dissipation and signal distortion. Above 400, the
bandwidth response will develop some peaking (for a gain of
two), but substantially higher resistor R2 values may be used
for higher voltage gains, such as up to 2k at a gain of eight
before peaking will develop. R1 and R3 are selected as
needed to set the voltage gain, and while R1 = R3 is sug-
gested, the gain equation above holds for any values (see
distortion for further suggestions).
Capacitance Considerations
As with many high bandwidth amplifiers, the EL2141 prefers
not to drive highly capacitive loads. It is best if the capaci-
tance on V
OUT
and V
OUTB
is kept below 10pF if the user
does not want gain peaking to develop.
In addition, on the EL2141, the two feedback nodes FBP and
FBN should be laid out so as to minimize stray capacitance,
else an additional pole will potentially develop in the
response with possible gain peaking.
FN7048 Rev 1.00
February 11, 2005
Page 4 of 6
EL2141
Typical Applications Circuits
FIGURE 7. TYPICAL TWISTED PAIR APPLICATION
FIGURE 8. DIFFERENTIAL LINE DRIVER WITH EQUALIZATION
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