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ADC08061/ADC08062 500 ns A/D Converter with S/H Function and Input Multiplexer
OBSOLETE
ADC08061/ADC08062
500 ns A/D Converter with S/H Function and Input
Multiplexer
General Description
NOTE: These products are obsolete. This data sheet is
provided for reference only.
Using a patented multi-step A/D conversion technique, the 8-
bit ADC08061 and ADC08062 CMOS ADCs offer 500 ns (typ)
conversion time, internal sample-and-hold (S/H), and dissi-
pate only 125 mW of power. The ADC08062 has a two-
channel multiplexer. The ADC08061/2 performs 8-bit conver-
sions using a multistep flash approach.
Input track-and-hold circuitry eliminates the need for an ex-
ternal sample-and-hold. The ADC08061/2 performs accurate
conversions of full-scale input signals that have a frequency
range of DC to 300 kHz (full-power bandwidth) without need
of an external S/H.
The digital interface has been designed to ease connection
to microprocessors and allows the parts to be I/O or memory
mapped.
July 15, 2009
Key Specifications
■
■
■
■
■
■
Resolution
Conversion Time
Full Power Bandwidth
Throughput rate
Power Consumption
Total Unadjusted Error
8 bits
560 ns max (WR-RD Mode)
300 kHz
1.5 MHz
100 mW max
±½ LSB and ±1 LSB
Features
■
■
■
■
■
1 or 2 input channels
No external clock required
Analog input voltage range from GND to V
+
Overflow output for cascading (ADC08061)
ADC08061 pin-compatible with the ADC0820
Applications
■
■
■
■
Mobile telecommunications
Hard disk drives
Instrumentation
High-speed data acquisition systems
Block Diagram
1108601
* ADC08061
** ADC08062
Ordering Information
Industrial (−40°C
≤
T
A
≤
85°C)
ADC08061BIN, ADC08062BIN
ADC08061CIWM, ADC08062CIWM
Package
N20A
M20B
© 2009 National Semiconductor Corporation
11086
Print Date/Time: 2009/07/15 15:48:35
www.national.com
11086 Version 6 Revision 2
ADC08061/ADC08062
Connection Diagrams
1108614
1108615
Dual-In-Line and Wide-Body
Small-Outline
Packages N20A or M20B
Dual-In-Line and Wide-Body
Small-Outline
Packages N20A or M20B
output latch. INT is reset by the rising edge of
RD.
This is the power supply ground pin. The
ground pin should be connected to a “clean”
ground reference point.
These are the reference voltage inputs. They
may be placed at any voltage between GND −
50 mV and V
+
+ 50 mV, but V
REF+
must be
greater than V
REF−
. Ideally, an input voltage
equal to V
REF−
produces an output code of 0,
and an input voltage greater than V
REF+
− 1.5
LSB produces an output code of 255.
For the ADC08062, an input voltage on any un-
selected input that exceeds V
+
by more than
100 mV or is below GND by more than 100 mV
will create errors in a selected channel that is
operating within proper operating conditions.
This is the active low Chip Select input. A logic
low signal applied to this input pin enables the
RD and WR inputs. Internally, the CS signal is
ORed with RD and WR signals.
Overflow Output. If the analog input is higher
than V
REF+
− ½ LSB, OFL will be low at the end
of conversion. It can be used when cascading
two ADC08061s to achieve higher resolution (9
bits). This output is always active and does not
go into TRI-STATE as DB0–DB7 do. When
OFL is set, all data outputs remain high when
the ADC08061's output data is read.
No connection.
This logic input is used to select one of the
ADC08062's input multiplexer channels. A
channel is selected as shown in the table below.
ADC08062
A0
0
1
Channel
V
IN1
V
IN2
Pin Descriptions
V
IN
,V
IN1–8
These are analog inputs. The input range is
GND–50 mV
≤
V
INPUT
≤
V
+
+ 50 mV. The
ADC08061 has a single input (V
IN
) and the
ADC08062 has a two-channel multiplexer
(V
IN1–2
).
TRI-STATE data outputs—bit 0 (LSB) through
bit 7 (MSB).
WR-RD Mode
(Logic high applied to MODE
pin)
WR:
With CS low, the conversion is started on
the falling edge of WR. The digital result will be
strobed into the output latch at the end of con-
version (see
Figures 2, 3, 4).
RD Mode
(Logic low applied to MODE pin)
RDY:
This is an open drain output (no internal
pull-up device). RDY will go low after the falling
edge of CS and return high at the end of con-
version.
Mode:
Mode (RD
or WR-RD)
selection input—
This pin is pulled to a logic low through an in-
ternal 50 µA current sink when left unconnect-
ed.
RD Mode
is selected if the MODE pin is left un-
connected or externally forced low. A complete
conversion is accomplished by pulling RD low
until output data appears.
WR-RD Mode
is selected when a high is ap-
plied to the MODE pin. A conversion starts with
the WR signal's rising edge and then using
RD to access the data.
WR-RD Mode
(logic high on the MODE pin)
This is the active low Read input. With a logic
low applied to the CS pin, the TRI-STATE data
outputs (DB0–DB7) will be activated when RD
goes low (Figures
2, 3, 4).
RD Mode
(logic low on the MODE pin)
With CS low, a conversion starts on the falling
edge of RD. Output data appears on DB0–DB7
at the end of conversion (see
Figures 1, 5).
This is an active low output that indicates that a
conversion is complete and the data is in the
2
11086 Version 6 Revision 2
GND
V
REF−
,V
REF+
DB0–DB7
WR /RDY
:
CS
MODE
OFL
NC
A0
RD
INT
V
+
Positive power supply voltage input. Nominal operating
supply voltage is +5V. The supply pin should be bypassed
with a 10 µF bead tantalum in parallel with a 0.1 ceramic
capacitor. Lead length should be as short as possible.
www.national.com
Print Date/Time: 2009/07/15 15:48:35
ADC08061/ADC08062
Absolute Maximum Ratings
(Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
+
)
Logic Control Inputs
Voltage at Other Inputs and Outputs
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Power Dissipation (Note 4)
All Packages
Storage Temperature
Lead Temperature (Note 5)
J Package (Soldering, 10 sec.)
N Package (Soldering, 10 sec.)
WM Package
(Vapor Phase, 60 sec.)
WM Package (Infrared, 15 sec.)
ESD Susceptibility (Note 6)
6V
−0.3V to
+ 0.3V
−0.3V to V
+
+ 0.3V
5 mA
20 mA
V
+
875 mW
−65°C to +150°C
+300°C
+260°C
+215°C
+220°C
2 kV
Operating Ratings
Temperature Range
Supply Voltage, (V
+
)
Pos. Reference Voltage, V
REF+
Neg. Reference Voltage, V
REF−
Input Voltage Range
(Notes 1, 2)
T
MIN
≤
T
A
≤
T
MAX
=
−40°C
≤
T
A
≤
85°C
+4.5V to +5.5V
(V
REF−
+ 1V) to V
+
GND to (V
REF+
− 1V)
V
REF−
to V
REF+
Converter Characteristics
The following specifications apply for RD Mode, V
+
= 5V, V
REF+
= 5V, and V
REF−
= GND unless otherwise specified.
Boldface
limits apply for T
A
= T
J
= T
MIN
to T
MAX
;
all other limits T
A
= T
J
= 25°C.
Symbol
INL
TUE
Parameter
Integral Non Linearity
Total Unadjusted Error
Missing Codes
Reference Input Resistance
V
REF+
V
REF−
V
IN
Positive Reference Input Voltage
Negative Reference Input
Voltage
Analog Input Voltage
(Note 10)
On Channel Input = 5V, Off Channel
Input = 0V (Note 11)
On Channel Input = 0V, Off Channel
Input = 5V (Note 11)
V
+
= 5V ±5%, V
REF
= 4.75V
All Codes Tested
−0.4
−0.4
±1/16
7.8
300
0.5
50
50
700
700
Conditions
ADC08061/2BIN
ADC08061/2CIWM
ADC08061/2BIN
ADC08061/2CIWM
Typical
(Note 7)
Limits
(Note 8)
±½
±1
±½
±1
0
500
1250
V
REF−
V
+
GND
V
REF+
GND − 0.1
V
+
+ 0.1
−20
−20
±½
Units
(Limit)
LSB (max)
LSB (max)
LSB (max)
LSB (max)
Bits (max)
Ω(min)
Ω (max)
V (min)
V (max)
V (min)
V (max)
V (min)
V (max)
µA (max)
µA (max)
LSB (max)
Bits
kHz
%
dB
dB
On Channel Input Current
PSS
Power Supply Sensitivity
Effective Bits
Full-Power Bandwidth
THD
S/N
IMD
Total Harmonic Distortion
Signal-to-Noise Ratio
Intermodulation Distortion
3
11086 Version 6 Revision 2
Print Date/Time: 2009/07/15 15:48:35
www.national.com
ADC08061/ADC08062
AC Electrical Characteristics
The following specifications apply for V
+
= 5V, t
r
= t
f
= 10 ns, V
REF+
= 5V, V
REF−
= 0V unless otherwise specified.
Boldface limits
apply for T
A
= T
J
= T
MIN
to T
MAX
;
all other limits T
A
= T
J
= 25°C.
Symbol
t
WR
t
RD
t
RDW
t
CONV
t
CRD
t
ACCO
Parameter
Write Time
Condition
Mode Pin to V
+
;
(Figures
2, 3, 4)
Typical
(Note 7)
100
350
200
400
500
655
640
Limits
(Note 8)
100
350
250
400
560
900
900
Units
(Limit)
ns (min)
ns (min)
ns (min)
ns (max)
ns (max)
ns (max)
ns (max)
Read Time (Time from Falling Edge of
Mode Pin to V
+
; (Figure
2)
WR to Falling Edge of RD )
RD Width
Mode Pin to GND; (Figure
5)
WR -RD Mode Conversion Time (t
WR
Mode Pin to V
+
; (Figure
2)
+ t
RD
+ t
ACC1
)
RD Mode Conversion Time
Mode Pin to GND; (Figure
1)
Access Time (Delay from Falling Edge C
L
≤
100 pF Mode Pin to GND;
of RD to Output Valid)
(Figure
1)
Mode Pin to V
+
, t
RD
≤
t
INTL
Access Time (Delay from Falling Edge (Figure
2)
C
L
= 10 pF
of RD to Output Valid)
C
L
≤
100 pF
t
RD
> t
INTL
; (Figures
3, 4)
C
L
≤
10 pF
C
L
= 100 pF
R
L
= 3 kΩ, C
L
= 10 pF
R
L
= 3 kΩ, C
L
= 10 pF
(Figures
3, 4)
Mode Pin = V
+
, C
L
= 50 pF
C
L
= 50 pF; (Figures 1, 2, 3, 4)2b,
and 4
)
C
L
= 50 pF; (Figure
4)
Mode Pin = 0V, C
L
= 50 pF, R
L
=
3 kΩ
(Figure
1)
R
L
= 3 kΩ, C
L
= 100 pF; (Figure
4)
Mode Pin = V
+
, t
RD
≤
t
INTL
; (Figure
3)
t
ACC1
45
50
110
ns (max)
ns
t
ACC2
Access Time (Delay from Falling Edge
of RD to Output Valid)
TRI-STATE Control (Delay from
Rising Edge of RD to HI-Z State)
TRI-STATE Control (Delay from
Rising Edge of RD to HI-Z State)
Delay from Rising Edge of
WR to Falling Edge of INT
Delay from Rising Edge of RD to
Rising Edge of INT
Delay from Rising Edge of WR to
Rising Edge of INT
Delay from CS to RDY
Delay from INT to Output Valid
Delay from RD to INT
25
30
30
30
520
50
45
25
0
60
50
10
0
0
0
25
5
5
55
ns (max)
t
0H
t
1H
t
INTL
t
INTH
t
INTH
t
RDY
t
ID
t
RI
t
N
t
AH
t
AS
t
CSS
t
CSH
C
VIN
C
OUT
C
IN
60
60
690
95
95
45
15
115
50
60
0
0
0
ns (max)
ns (max)
ns (max)
ns (max)
ns (max)
ns (max)
ns (max)
ns (max)
ns (min)
ns (min)
ns (max)
ns (max)
ns (min)
pF
pF
pF
Time between End of RD and Start of
(Figures
1, 2, 3, 4, 5)
New Conversion
Channel Address Hold Time
Channel Address Setup Time
CS Setup Time
CS Hold Time
Analog Input Capacitance
Logic Output Capacitance
Logic Input Capacitance
(Figures
1, 2, 3, 4, 5)
(Figures
1, 2, 3, 4, 5)
(Figures
1, 2, 3, 4, 5)
(Figures
1, 2, 3, 4, 5)
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4
Print Date/Time: 2009/07/15 15:48:35
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