Ordering number : ENN7678
Monolithic Digital IC
LB11875
Three-Phase Brushless Motor Driver
for Polygonal Mirror Motors
Overview
The LB11875 is a pre-driver IC developed for driving
motors such as the polygonal mirror motor used in laser
printers. A motor drive circuit with high rotational
precision can be implemented by using either a driver
array or discrete transistors (FETs) at the LB11875’s
outputs. The LB11875 achieves low power even at large
currents by adopting direct PWM drive.
Package Dimensions
unit: mm
3247A-SSOP36
[LB11875]
36
19
•
•
•
•
•
•
•
Three-phase bipolar drive (direct PWM drive)
PLL speed control circuit
Speed control by an external clock signal
Supports Hall sensor FG operation
Clock divisor switching function
Phase lock state detection output (with mask function)
Inculudes current limiter, thermal protection, rotor
constraint protection, and low-voltage protection
circuits.
1
0.3
18
0.2
15.0
SANYO: SSOP36 (275 mil)
Specifications
Absolute Maximum Ratings
at Ta = 25°C
Parameter
Supply voltage
Input current
Output current
Allowable power dissipation 1
Allowable power dissipation 2
Operating temperature
Storage temperature
Symbol
V
CC
max
I13 max
I
O
max
Pd max1
Pd max2
Topr
Tstg
Pin V13
UL, VL, WL, UH, VH, and WH pins
Independent IC
Mounted on a PWB (114.3
×
76.1
×
1.6 mm, glass epoxy)
Conditions
Ratings
18
5
30
0.62
1.36
–20 to +80
–55 to +150
Unit
V
mA
mA
W
W
°C
°C
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
12004TN (OT) No. 7678-1/16
0.1
(0.7)
0.8
1.7max
(1.5)
0.5
Features and Functions
5.6
7.6
LB11875
Allowable Operating Ranges
at Ta = 25°C
Parameter
Supply voltage range 1
Supply voltage range 2
Input current range
Output current
5 V regulator-voltage output current
LD pin applied voltage
LD pin output current
FGS pin applied voltage
FGS pin output current
Symbol
V
CC
1
V
CC
2
I13
IO
IREG
VLD
ILD
VFGS
IFGS
When V
CC
is shorted to VREG
Pin V13
UL, VL, WL, UH, VH, and WH pins
Conditions
Ratings
8 to 17
4.5 to 5.5
0.5 to 4
20
0 to –30
0 to 17
0 to 15
0 to 17
0 to 10
Unit
V
V
mA
mA
mA
V
mA
V
mA
Electrical Characteristics
at Ta = 25°C, V
CC
= 12 V
Parameter
Current drain 1
Current drain 2
[5 V ragulator-Voltage Output (VREG pin)]
Output voltage
Voltage regulation
Load regulation
Temperature coefficient
[13 V ragulator-Voltage Output (V13 pin)]
Output voltage
[Output Block]
Output saturation voltage 1-1
Output saturation voltage 1-2
Output saturation voltage 2
Output leakage current
[Hall Amplifier Block]
Input bias current
Common-phase input voltage range 1
Common-phase input voltage range 2
Input sensitivity
Hysteresis width
Input voltage low
→
high
Input voltage high
→
low
[FG Schmitt Block]
Input bias current
Common-phase input voltage range 1
Common-phase input voltage range 2
Input sensitivity
Hysteresis width
Input voltage low
→
high
Input voltage high
→
low
[FGS output]
Output saturation voltage
Output leakage current
[PWM Oscillator]
High-level output voltage
Low-level output voltage
External capacitor charge current
Oscillator frequency
Amplitude
VOH (PWM)
VOL (PWM)
ICHG
f (PWM)
V (PWM)
VPWM = 2.0 V
C = 620 pF
1.0
2.6
1.4
–65
2.9
1.7
–50
50
1.2
1.4
3.2
2.0
–35
V
V
µA
kHz
Vp-p
VOL (FGS)
IL (FGS)
ILD = 7 mA
VO = V
CC
0.15
0.5
10
V
µA
IB (FGS)
VICM1 (FGS) When Hall-effect sensors are used
VICM2 (FGS) When one input side is biased (a Hall IC is used)
VIN (FGS)
∆VIN
(FGS)
VSLH (FGS)
VSHL (FGS)
Sine wave
Design target value
Design target value
Design target value
–2
0.5
0
50
15
24
12
–12
42
–0.5
V
CC
– 2.0
V
CC
µA
V
V
mVp-p
mV
mV
mV
∆VIN
(HA)
VSLH (HA)
VSHL (HA)
IHB (HA)
VICM1 (HA)
VICM2 (HA)
When Hall-effect sensors are used
When one input side is biased (a Hall IC is used)
Sine wave
–2
0.5
0
50
15
24
12
–12
42
–0.5
V
CC
– 2.0
V
CC
µA
V
V
mVp-p
mV
mV
mV
Vosat1-1
Vosat1-2
Vosat2
Ioleak
Low level, I
O
= 400 µA
Low level, I
O
= 10 mA
High level, I
O
= –20 mA
V
CC
– 1.2
0.2
0.9
V
CC
– 0.9
10
0.5
1.2
V
V
V
µA
V13
I
O
= 2 mA
12.5
13.5
14.5
V
VREG
∆VREG1
∆VREG2
∆VREG3
V
CC
= 8 to 13.5 V
I
O
= 0 to –15 mA
Design target value
4.65
5.0
40
20
0
5.35
100
100
V
mV
mV
mV/°C
Symbol
I
CC
1
I
CC
2
In stop mode
Conditions
Ratings
min
typ
15
3
max
25
5
Unit
mA
mA
Continued on next page.
No. 7678-2/16
LB11875
Continued from preceding page.
Parameter
[CSD Oscillator]
High-level output voltage
Low-level output voltage
External capacitor charge current 1
External capacitor charge current 2
Oscillator frequency
Amplitude
[Phase Comparator Output]
High-level output voltage
Low-level output voltage
Output source current
Output sink current
[Phase Lock Detection Output]
Output saturation voltage
Output leakage current
[Error Amplifier (ERR) Block]
Input offset voltage
Input bias current
High-level output voltage
Low-level output voltage
DC bias level
[Current Limiter Circuit]
Limiter voltage
[Low-voltage Protection Circuit]
Operating voltage
Release voltage
Hysteresis width
[Thermal Shutdown Operation]
Thermal shutdown operating temperature
Hysteresis width
[CLD Circuit]
External capacitor charge current
Operating voltage
[CLKIN Pin]
External signal input frequency
High-level input voltage
Low-level input voltage
Input open voltage
Hysteresis width
High-level input current
Low-level input current
[S/S Pin]
High-level input voltage
Low-level input voltage
Input open voltage
Hysteresis width
High-level input current
Low-level input current
VIH (SS)
VIL (SS)
VIO (SS)
VIS (SS)
IIH (SS)
IIL (SS)
VS/S = VREG
VS/S = 0 V
2.0
0
VREG – 0.5
0.13
–10
–130
0.21
0
–90
VREG
1.0
VREG
0.29
+10
V
V
V
V
µA
µA
fI (CKIN)
VIH (CKIN)
VIL (CKIN)
VIO (CKIN)
VIS (CKIN)
IIH (CKIN)
IIL (CKIN)
VCKIN = VREG
VCKIN = 0 V
0.1
2.0
0
VREG – 0.5
0.13
–10
–130
0.21
0
–90
10
VREG
1.0
VREG
0.29
+10
kHz
V
V
V
V
µA
µA
ICLD
VH (CLD)
–5
3.25
–4
3.5
–3
3.75
µA
V
TSD
∆TSD
Design target value (junction temperature)
Design target value (junction temperature)
150
180
30
°C
°C
VSDL
VSDH
∆VSD
3.5
4.0
0.35
3.7
4.2
0.5
3.9
4.4
0.65
V
V
V
VRF
0.225
0.25
0.275
V
VIO (ER)
IB (ER)
VOH (ER)
VOL (ER)
VB (ER)
IEI = –0.1 mA, no load
IEI = 0.1 mA, no load
Design target value
–5%
Design target value
–10
–0.4
3.7
1.3
VREG/2
+5%
+10
+0.4
mV
µA
V
V
V
VOL (LD)
IL (LD)
ILD = 10 mA
VO = V
CC
0.15
0.4
10
V
µA
VPDH
VPDL
IPD+
IPD–
IOH = –100 µA
IOH = 100 µA
VPD = VREG/2
VPD = VREG/2
1.5
VREG – 0.2
VREG – 0.1
0.2
0.3
–0.6
V
V
mA
mA
VOH (CSD)
VOL (CSD)
ICHG1
ICHG2
f (CSD)
V (CSD)
C = 0.068 µF
2.2
3.2
0.9
–13
7
3.5
1.1
–10
10
30
2.4
2.6
3.8
1.3
–7
13
V
V
µA
µA
Hz
Vp-p
Symbol
Conditions
Ratings
min
typ
max
Unit
Continued on next page.
No. 7678-3/16
LB11875
Continued from preceding page.
Parameter
[F/R Pin]
High-level input voltage
Low-level input voltage
Input open voltage
Hysteresis width
High-level input current
Low-level input current
[BRSEL Pin]
High-level input voltage
Low-level input voltage
Input open voltage
Hysteresis width
High-level input current
Low-level input current
[CLKSEL Pin]
High-level input voltage
Low-level input voltage
Input open voltage
Hysteresis width
High-level input current
Low-level input current
VIH (CSEL)
VIL (CSEL)
VIO (CSEL)
VIS (CSEL)
IIH (CSEL)
IIL (CSEL)
VCSEL = VREG
VCSEL = 0 V
2.0
0
VREG – 0.5
0.13
–10
–130
0.21
0
–90
VREG
1.0
VREG
0.29
+10
V
V
V
V
µA
µA
VIH (BSEL)
VIL (BSEL)
VIO (BSEL)
VIS (BSEL)
IIH (BSEL)
IIL (BSEL)
VBSEL = VREG
VBSEL = 0 V
2.0
0
VREG – 0.5
0.13
–10
–130
0.21
0
–90
VREG
1.0
VREG
0.29
+10
V
V
V
V
µA
µA
VIH (FR)
VIL (FR)
VIO (FR)
VIS (FR)
IIH (FR)
IIL (FR)
VF/R = VREG
VF/R = 0 V
2.0
0
VREG – 0.5
0.13
–10
–130
0.21
0
–90
VREG
1.0
VREG
0.29
+10
V
V
V
V
µA
µA
Symbol
Conditions
Ratings
min
typ
max
Unit
Three-Phase Logic Truth Table
(IN = H indicates the state where IN+ > IN–.)
F/R = Low
IN1
1
2
3
4
5
6
H
H
H
L
L
L
IN2
L
L
H
H
H
L
IN3
H
L
L
L
H
H
IN1
L
L
L
H
H
H
F/R = High
IN2
H
H
L
L
L
H
IN3
L
H
H
H
L
L
Output
Source
VH
WH
WH
UH
UH
VH
Sink
UL
UL
VL
VL
WL
WL
S/S Pin
Input state
High or open
Low
State
Stop
Start
BRSEL pin
Input state
High or open
Low
When braking
Free running
Short-circuit braking
CLKSEL pin
Input state
High or open
Low
fFG = fCLK
÷
<divisor>
Clock divisor
1
2
No. 7678-4/16
LB11875
Pin Assignment
RFGND
FGIN+
FGIN–
IN1+
IN2+
IN3+
IN1–
IN2–
IN3–
GND
20
17
V13
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
19
LB11875
1
CLK
2
FGS
3
LD
4
S/S
5
CLKSEL
6
BRSEL
7
F/R
8
PD
9
EI
10
EO
11
TOC
12
NC
13
PWM
14
CLD
15
CSD
16
VREG
18
LVSD
No. 7678-5/16
Pd max — Ta
2.0
Allowable power dissipation, Pdmax — W
1.5
1.36 W
Mounted on a PWB (114.3
×
76.1
×
1.6 mm, glass epoxy)
1.0
0.62 W
0.5
0.347 W
0
–20
Independent IC
0.761 W
0
20
40
60
80
100
Ambient temperature, Ta —
°C
V
CC
WH
WL
UH
VH
RF
UL
VL
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