IBM13M16734BCB-75AT datasheet, PDF

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IBM13M16734BCB-75AT: DescriptionSynchronous DRAM Module, 16MX72, 5.65ns, CMOS, DIMM-168; Categorystorage storage; File Size754KB，20 Pages; ManufacturerIBM; Websitehttp://www.ibm.com

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IBM13M16734BCB-75AT Overview

Synchronous DRAM Module, 16MX72, 5.65ns, CMOS, DIMM-168

IBM13M16734BCB-75AT Parametric

Parameter Name	Attribute value
Maker	IBM
Parts packaging code	DIMM
package instruction	DIMM, DIMM168
Contacts	168
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	5.65 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	133 MHz
I/O type	COMMON
JESD-30 code	R-XDMA-N168
memory density	1207959552 bit
Memory IC Type	SYNCHRONOUS DRAM MODULE
memory width	72
Number of functions	1
Number of ports	1
Number of terminals	168
word count	16777216 words
character code	16000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	16MX72
Output characteristics	3-STATE
Package body material	UNSPECIFIED
encapsulated code	DIMM
Encapsulate equivalent code	DIMM168
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
power supply	3.3 V
Certification status	Not Qualified
refresh cycle	4096
self refresh	YES
Maximum standby current	0.033 A
Maximum slew rate	2.79 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	NO LEAD
Terminal pitch	1.27 mm
Terminal location	DUAL

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IBM13M16734BCB

16M x 72 1-Bank Registered SDRAM Module

Features

• 168-Pin Registered 8-Byte Dual In-Line Memory

Module

• 16Mx72 Synchronous DRAM DIMM

-75A

Reg.

133

7.5

5.65

100

10.0

5.65

Units

MHz

DIMM CAS Latency

Clock Frequency

Clock Cycle

Clock Access Time

•

Intended for 100MHz and 133MHz applications

Inputs and outputs are LVTTL (3.3V) compatible

Single 3.3V

0.3V power supply

Single Pulsed RAS interface

SDRAMs have four internal banks

Module has one physical bank

Fully synchronous to positive clock edge

• Programmable operation:

- DIMM CAS Latency: 4 (Registered mode);

- Burst Type: Sequential or Interleave

- Burst Length: 1, 2, 4, 8, and Full-Page

- Operation: Burst Read and Write or Multiple

Burst Read with Single Write

• Data Mask for Byte Read/Write control

• Auto Refresh (CBR) and Self Refresh

• Automatic and controlled Precharge commands

• Suspend mode and Power Down mode

• 12/10/2 Addressing (Row/Column/Bank)

• 4096 refresh cycles distributed across 64ms

• Card size: 5.25" x 1.70" x 0.157"

• Gold contacts

• DRAMs in TSOP - Type II Package

• Serial Presence Detect with Write protect fea-

ture

Description

IBM13M16734BCB is a registered 168-Pin Syn-

chronous DRAM Dual In-Line Memory Module

(DIMM) organized as a 16Mx72 high-speed mem-

ory array. The DIMM uses 18 16Mx4 SDRAMs in

400 mil TSOP packages. The DIMM achieves high-

speed data-transfer rates of 100MHz and 133MHz

by employing a prefetch/pipeline hybrid architecture

that synchronizes the output data to a system clock.

The DIMM is intended for use in applications oper-

ating at 100MHz and 133MHz memory bus speeds.

All control and address signals are re-driven

through registers/buffers to the SDRAM devices.

Operating in registered mode (REGE pin tied high),

the control/address input signals are latched in the

SDRAM devices on the following rising clock edge

(data access is delayed by one clock).

A phase-lock loop (PLL) on the DIMM is used to re-

drive the clock signals to both the SDRAM devices

and the registers to minimize system clock loading.

(CK0 is connected to the PLL, and CK1, CK2, and

CK3 are terminated on the DIMM). A single clock

enable (CKE0) controls all devices on the DIMM,

enabling the use of SDRAM Power Down modes.

Prior to any access operation, the device CAS

latency and burst type/length/operation type must

be programmed into the DIMM by address inputs

A0-A9 using the mode register set cycle. The DIMM

CAS latency when operated in Registered mode is

one clock later than the device CAS latency due to

the address and control signals being clocked to the

SDRAM devices.

The DIMM uses serial presence detects imple-

mented via a serial EEPROM using the two-pin IIC

protocol. The first 128 bytes of serial PD data are

programmed and locked by the DIMM manufac-

turer. The last 128 bytes are available to the cus-

tomer and may be write protected by providing a

high level to pin 81 on the DIMM. An on-board pull-

down resistor keeps this in the Write Enable mode.

All IBM 168-pin DIMMs provide a high-performance,

flexible 8-byte interface in a 5.25" long space-saving

footprint.

19L7298.F38443A

8/99

Use is further subject to the provisions at the end of this document.

Page 1 of 20

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