FQD3N50C / FQU3N50C 500V N-Channel MOSFET
March 2008
QFET
FQD3N50C / FQU3N50C
500V N-Channel MOSFET
Features
•
•
•
•
•
•
•
2.5A, 500V, R
DS(on)
= 2.5Ω @V
GS
= 10 V
Low gate charge ( typical 10 nC)
Low Crss ( typical 8.5pF)
Fast switching
100% avalanche tested
Improved dv/dt capability
RoHS compliant
®
Description
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary, planar
stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the avalanche
and commutation mode. These devices are well suited for high
efficient switched mode power supplies, active power factor
correction, electronic lamp ballast based on half bridge
topology.
D
D
G
G
S
D-PAK
FQD Series
I-PAK
G D S
FQU Series
S
Absolute Maximum Ratings
Symbol
V
DSS
I
D
I
DM
V
GSS
E
AS
I
AR
E
AR
dv/dt
P
D
T
J
, T
STG
T
L
Drain-Source Voltage
Drain Current
- Continuous (T
C
= 25°C)
- Continuous (T
C
= 100°C)
Drain Current
- Pulsed
(Note 1)
Parameter
FQD3N50C/FQU3N50C
500
2.5
1.5
10
±
30
(Note 2)
(Note 1)
(Note 1)
(Note 3)
Units
V
A
A
A
V
mJ
A
mJ
V/ns
W
W/°C
°C
°C
Gate-Source Voltage
Single Pulsed Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Power Dissipation (T
C
= 25°C)
- Derate above 25°C
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
200
2.5
3.5
4.5
35
0.28
-55 to +150
300
Thermal Characteristics
Symbol
R
θJC
R
θJA
R
θJA
Parameter
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient*
Thermal Resistance, Junction-to-Ambient
Typ
--
--
--
Max
3.5
50
110
Units
°C/W
°C/W
°C/W
* When mounted on the minimum pad size recommended (PCB Mount)
©2008 Fairchild Semiconductor Corporation
1
www.fairchildsemi.com
FQD3N50C / FQU3N50C Rev. B
FQD3N50C / FQU3N50C 500V N-Channel MOSFET
Package Marking and Ordering Information
Device Marking
FQD3N50C
FQD3N50C
FQU3N50C
Device
FQD3N50CTM
FQD3N50CTF
FQU3N50CTU
Package
D-PAK
D-PAK
I-PAK
Reel Size
380mm
380mm
-
Tape Width
16mm
16mm
-
Quantity
2500
2500
70
Electrical Characteristics
Symbol
Off Characteristics
BV
DSS
∆BV
DSS
/
∆T
J
I
DSS
I
GSSF
I
GSSR
V
GS(th)
R
DS(on)
g
FS
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
gs
Q
gd
T
C
= 25°C unless otherwise noted
Parameter
Drain-Source Breakdown Voltage
Breakdown Voltage Temperature Coefficient
Zero Gate Voltage Drain Current
Test Conditions
V
GS
= 0 V, I
D
= 250
µA
I
D
= 250
µA,
Referenced to 25°C
V
DS
= 500 V, V
GS
= 0 V
V
DS
= 400 V, T
C
= 125°C
V
GS
= 30 V, V
DS
= 0 V
V
GS
= -30 V, V
DS
= 0 V
V
DS
= V
GS
, I
D
= 250
µA
V
GS
= 10 V, I
D
= 1.25 A
V
DS
= 40 V, I
D
= 1.25 A
V
DS
= 25 V, V
GS
= 0 V,
f = 1.0 MHz
(Note 4)
Min
500
--
--
--
--
--
Typ
--
0.7
--
--
--
--
Max Units
--
--
1
10
100
-100
V
V/°C
µA
µA
nA
nA
Gate-Body Leakage Current, Forward
Gate-Body Leakage Current, Reverse
On Characteristics
Gate Threshold Voltage
Static Drain-Source On-Resistance
Forward Transconductance
2.0
--
--
--
2.1
1.5
4.0
2.5
--
V
Ω
S
Dynamic Characteristics
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
--
--
--
280
50
8.5
365
65
11
pF
pF
pF
Switching Characteristics
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
(Note 4, 5)
V
DD
= 250 V, I
D
= 2.5A,
R
G
= 25
Ω
--
--
--
--
10
25
35
25
10
1.5
5.5
30
60
80
60
13
--
--
ns
ns
ns
ns
nC
nC
nC
Turn-Off Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
V
DS
= 400 V, I
D
= 2.5A,
V
GS
= 10 V
(Note 4, 5)
--
--
--
Drain-Source Diode Characteristics and Maximum Ratings
I
S
I
SM
V
SD
t
rr
Q
rr
NOTES:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 58mH, I
AS
=2.5A, V
DD
= 50V, R
G
= 25
Ω,
Starting T
J
= 25°C
3. I
SD
≤
2.5A, di/dt
≤200A/µs,
V
DD
≤
BV
DSS,
Starting T
J
= 25°C
4. Pulse Test : Pulse width
≤
300µs, Duty cycle
≤
2%
5. Essentially independent of operating temperature
Maximum Continuous Drain-Source Diode Forward Current
Maximum Pulsed Drain-Source Diode Forward Current
Drain-Source Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
V
GS
= 0 V, I
S
= 2.5 A
V
GS
= 0 V, I
S
= 3 A,
dI
F
/ dt = 100 A/µs
(Note 4)
--
--
--
--
--
--
--
--
170
0.7
2.5
10
1.4
--
--
A
A
V
ns
µC
2
FQD3N50C / FQU3N50C Rev. B
www.fairchildsemi.com
FQD3N50C / FQU3N50C 500V N-Channel MOSFET
Typical Performance Characteristics
Figure 1. On-Region Characteristics
Figure 2. Transfer Characteristics
10
V
GS
Top :
1
1
10
I
D
, Drain Current [A]
I
D
, Drain Current [A]
15.0 V
10.0 V
8.0 V
7.0 V
6.5 V
6.0 V
5.5 V
Bottom : 5.0 V
150
°
C
10
0
10
0
25
°
C
-55
°
C
10
-1
Notes :
1. 250
µ
s Pulse Test
2. T
C
= 25
°
C
-1
Note
1. V
DS
= 40V
2. 250
µ
s Pulse Test
10
-1
10
10
0
10
1
2
4
6
8
10
V
DS
, Drain-Source Voltage [V]
V
GS
, Gate-Source Voltage [V]
Figure 3. On-Resistance Variation vs.
Drain Current and Gate Voltage
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current
and Temperatue
8.0
7.5
R
DS(ON)
[
Ω
],
Drain-Source On-Resistance
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
0
2
4
6
8
10
Note : T
J
= 25
°
C
V
GS
= 10V
I
DR
, Reverse Drain Current [A]
10
0
V
GS
= 20V
150
°
C
25
°
C
Notes :
1. V
GS
= 0V
2. 250
µ
s Pulse Test
10
-1
0.2
0.4
0.6
0.8
1.0
1.2
1.4
I
D
, Drain Current [A]
V
SD
, Source-Drain voltage [V]
Figure 5. Capacitance Characteristics
C
iss
= C
gs
+ C
gd
(C
ds
= shorted)
C
oss
= C
ds
+ C
gd
Figure 6. Gate Charge Characteristics
12
600
C
rss
= C
gd
10
V
GS
, Gate-Source Voltage [V]
V
DS
= 100V
V
DS
= 250V
V
DS
= 400V
Capacitances [pF]
C
iss
400
8
C
oss
6
200
C
rss
Note ;
1. V
GS
= 0 V
2. f = 1 MHz
4
2
Note : I
D
= 3A
0
-1
10
0
10
0
10
1
0
5
10
V
DS
, Drain-Source Voltage [V]
Q
G
, Total Gate Charge [nC]
3
FQD3N50C / FQU3N50C Rev. B
www.fairchildsemi.com
FQD3N50C / FQU3N50C 500V N-Channel MOSFET
Typical Performance Characteristics
(Continued)
Figure 7. Breakdown Voltage Variation
vs. Temperature
Figure 8. On-Resistance Variation
vs. Temperature
1.2
3.0
BV
DSS
, (Normalized)
Drain-Source Breakdown Voltage
1.1
R
DS(ON)
, (Normalized)
Drain-Source On-Resistance
2.5
2.0
1.0
1.5
1.0
0.9
Notes :
1. V
GS
= 0 V
2. I
D
= 250
µ
A
0.5
Notes :
1. V
GS
= 10 V
2. I
D
= 1.5 A
0.8
-100
-50
0
50
100
150
200
0.0
-100
-50
0
50
100
150
200
T
J
, Junction Temperature [
°
C]
T
J
, Junction Temperature [
°
C]
Figure 9. Maximum Safe Operating Area
Figure 10. Maximum Drain Current
vs. Case Temperature
3
10
2
Operation in This Area
is Limited by R
DS(on)
I
D
, Drain Current [A]
10
0
100
µ
s
1 ms
10 ms
100 ms
DC
Notes :
1. T
C
= 25
°
C
2. T
J
= 150
°
C
3. Single Pulse
I
D
, Drain Current [A]
10
3
10
1
2
1
10
-1
10
-2
10
0
10
1
10
2
0
25
50
75
100
125
150
V
DS
, Drain-Source Voltage [V]
T
C
, Case Temperature [
°
C]
Figure 11. Transient Thermal Response Curve
Z
θ
JC
(t), Thermal Response
D = 0 .5
10
0
0 .2
0 .1
0 .0 5
N o te s :
1 . Z
θ
JC
(t) = 3 .5
°
C /W M ax.
2 . D uty F ac to r, D = t
1
/t
2
3 . T
JM
- T
C
= P
D M
* Z
θ
JC
(t)
10
-1
0 .0 2
0 .0 1
sin gle p u ls e
P
DM
t
1
t
2
10
-2
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
t
1
, S q u a re W a ve P u ls e D u ra tio n [s e c ]
4
FQD3N50C / FQU3N50C Rev. B
www.fairchildsemi.com
FQD3N50C / FQU3N50C 500V N-Channel MOSFET
Gate Charge Test Circuit & Waveform
Resistive Switching Test Circuit & Waveforms
Unclamped Inductive Switching Test Circuit & Waveforms
5
FQD3N50C / FQU3N50C Rev. B
www.fairchildsemi.com
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