Preliminary
GS880V37BT-333/300/275/250/225/200
100-Pin TQFP
Commercial Temp
Industrial Temp
Features
• Single Cycle Deselect (SCD) operation
• 1.8 V +10%/–10% core power supply
• 1.8 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP package
-333 -300 -275 -250 -225 -200 Unit
2.0 2.2 2.3 2.3 2.5 2.7 ns
3.0 3.3 3.6 4.0 4.4 5.0 ns
395
360
330 300 270 mA
256K x 36
9Mb Sync Burst SRAMs
Byte Write and Global Write
333 MHz–200 MHz
1.8 V V
DD
1.8 V I/O
their outputs immediately after the deselect command has been
captured in the input registers.
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS880V37BT operates on a 1.8 V power supply. All input
are 1.8 V compatible. Separate output power (V
DDQ
) pins are
used to decouple output noise from the internal circuits and are
1.8 V compatible.
Pipeline
3-1-1-1
1.8 V
t
KQ
tCycle
Curr
(x32/x36)
435
Functional Description
Applications
The GS880V37BT is a 9,437,184-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications,
ranging from DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
SCD Pipelined Reads
The GS880V37BT is a SCD (Single Cycle Deselect) pipelined
synchronous SRAM. DCD (Dual Cycle Deselect) versions are
also available. SCD SRAMs pipeline deselect commands one
stage less than read commands. SCD RAMs begin turning off
Rev: 1.00 1/2003
1/19
© 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880V37BT-333/300/275/250/225/200
TQFP Pin Description
Symbol
A
0
, A
1
A
2
–A
17
A
18
DQ
A1
–DQ
A9
DQ
B1
–DQ
B9
DQ
C1
–DQ
C9
DQ
D1
–DQ
D98
NC
BW
B
A
, B
B
B
C
, B
D
CK
GW
E
1
, E
3
E
2
G
ADV
ADSP, ADSC
ZZ
LBO
V
DD
V
SS
V
DDQ
V
DDQ
/DNU
Type
I
I
I
I/O
—
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
—
Description
Address field LSBs and Address Counter preset Inputs
Address Inputs
Address Input
Data Input and Output pins
No Connect
Byte Write—Writes all enabled bytes; active low
Byte Write Enable for DQ
A
, DQ
B
Data I/Os; active low
Byte Write Enable for DQ
C
, DQ
D
Data I/Os; active low
Clock Input Signal; active high
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
Chip Enable; active high
Output Enable; active low
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep Mode control; active high
Linear Burst Order mode; active low
Core power supply
I/O and Core Ground
Output driver power supply
V
DDQ
or V
DD
(must be tied high)
or
Do Not Use (must be left floating)
Rev: 1.00 1/2003
3/19
© 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880V37BT-333/300/275/250/225/200
Mode Pin Functions
Mode Name
Burst Order Control
Power Down Control
Pin
Name
LBO
ZZ
State
L
H
L or NC
H
Function
Linear Burst
Interleaved Burst
Active
Standby, I
DD
= I
SB
Note:
Thereis a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in the
above tables.
Burst Counter Sequences
Linear Burst Sequence
I
nterleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
2nd address
3rd address
4th address
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
01
10
11
00
10
11
00
01
11
00
01
10
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
2nd address
3rd address
4th address
00
01
10
11
Note: The burst counter wraps to initial state on the 5th clock.
Note: The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Byte Write Truth Table
Function
Read
Read
Write byte a
Write byte b
Write byte c
Write byte d
Write all bytes
Write all bytes
GW
H
H
H
H
H
H
H
L
BW
H
L
L
L
L
L
L
X
B
A
X
H
L
H
H
H
L
X
B
B
X
H
H
L
H
H
L
X
B
C
X
H
H
H
L
H
L
X
B
D
X
H
H
H
H
L
L
X
Notes
1
1
2, 3
2, 3
2, 3
2, 3
2, 3
Notes:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
2. Byte Write Enable inputs B
A
, B
B
, B
C
and/or B
D
may be used in any combination with BW to write single or multiple bytes.
3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
Rev: 1.00 1/2003
5/19
© 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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