TDL2R-433-4 datasheet, PDF - EEWORLD Datasheet

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TDL2R-433-4: DescriptionUHF Multi Channel Transparent Data Link Transceiver; CategoryWireless rf/communication Telecom circuit; File Size350KB，11 Pages; ManufacturerRadiometrix Ltd.; Websitehttp://www.radiometrix.com/

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TDL2R-433-4 Overview

UHF Multi Channel Transparent Data Link Transceiver

TDL2R-433-4 Parametric

Parameter Name	Attribute value
Maker	Radiometrix Ltd.
package instruction	, MODULE,12LEAD,1.2
Reach Compliance Code	unknow
Number of terminals	12
Maximum operating temperature	70 °C
Minimum operating temperature	-20 °C
Package body material	METAL
Encapsulate equivalent code	MODULE,12LEAD,1.2
power supply	5 V
Certification status	Not Qualified
Nominal supply voltage	5 V
Temperature level	COMMERCIAL

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Issue 3, 06 October 2006

Radiometrix

Hartcran House, 231 Kenton Lane, Harrow, HA3 8RP, England

Tel: +44 (0) 20 8909 9595, Fax: +44 (0) 20 8909 2233

TDL2A

UHF Multi Channel Transparent Data Link Transceiver

The TDL2A is a 9600baud half-duplex multi

channel OEM radio modem in BiM2

footprint, operating on European 433MHz

ISM band. TLD2A acts as a transparent

serial cable to attached host. TDL2A is an

intermediate level OEM radio modem which

is in between a raw FM radio module like

BiM2 and a sophisticated OEM radio

modem like SPM2. It takes care of

preamble, synchronisation, bit balancing

and error checking along with automatic

noise squelching.

Figure 1: TDL2A-433-9 radio modem

The TDL2A provides a half duplex link. Provided no two devices attempt to transmit simultaneously no

further restrictions on data transmission need be made, as all transmit timing, valid data identification

and datastream buffering is conducted by the unit. Synchronisation and framing words in the packet

prevent the receiver outputting garbage in the absence of wanted RF signal or presence of interference.

For multiple radio systems (polled networks) a TDL2A can be set to 1 of 8 unique addresses. As well as

having unique addresses, the TDL2A allows operation on one of 5 pre-set frequencies in the 433MHz

band. These frequencies are non-overlapping and simultaneous operation of TDL2As in the same area

on different channels will be possible. Units are supplied on 433.925MHz (Ch0) as default.

Features

•

Conforms to EN 300 220-3 and EN 301 489-3

High quality, stable crystal reference

Low noise synthesiser / VCO

SAW front-end filter

Multi-stage ceramic IF filtering

Single conversion superhet

Serial modem baud rate at 9600bps (half-duplex)

Addressable point-to-point

5 serial select wideband channels

Available as TDL2T transmitter and TDL2R receiver for one way communication

Applications

•

PDAs, organisers & laptops

Handheld / portable terminals

EPOS equipment, barcode scanners

In-building environmental monitoring and control

Remote data acquisition system, data logging

Fleet management, vehicle data acquisition

Technical Summary

•

Operating frequency: 433.925MHz (default)

Modulation: 16kbps bi-phase FSK

Supply: 5V at 28mA transmit, 22mA receive/idle

Transmit power: +10dBm (10mW)

Receiver sensitivity: -107dBm (for 1% BER)

32 byte data buffer

Adjacent channel rejection: 65db @ ±320kHz

Receiver Blocking: 84dB

TDL2A Data Sheet

page 1

Radiometrix Ltd

SETUP

pin 15

Active low input to enter configuration or diagnostic test mode. It has a 47kΩ pull-ups to Vcc

TXD

pin 14

This is inverted RS232 data input at 5V CMOS logic level. It can be directly interfaced to data output of

a UART in a microcontroller or to a TXD pin of an RS232 serial port via a MAX232 or equivalent

RS232-CMOS level converter. TXD does not have an internal pull-up. If TDL2A is used in Receive only

mode, TXD should be tied to Vcc.

pin 13

There is no pin in this position.

RXD

pin 12

This is inverted RS232 data output at 5V CMOS logic level. It can be directly interfaced to data input of

a UART in a microcontroller or to a RXD pin of an RS232 serial port via a MAX232 or equivalent

RS232-CMOS level converter.

pin 11

STATUS

This pin goes high when valid data is present in the receive buffer. It can be used to trigger an

interrupt in the host to download received data packet instead of waiting for it. It can be also be used as

a primitive CTS signal. It is inverted RS232 data output at 5V CMOS logic level. It can be directly

interfaced to an input of a microcontroller as a Data Detect (DD) or to CTS, DSR, DCD pins of an RS232

serial port via a MAX232 or equivalent RS232-CMOS level converter. This is can only be used to

prevent host from uploading any data before downloading already received data, because transmission

is prioritised over reception and any data to be transmitted will erase received data which is in the

common buffer.

Serial interface – modem operation

To connect to a true RS232 device, inverting RS232-CMOS level shifters must be used. Maxim MAX232

or equivalent are ideal, but simple NPN transistor switches with pull-ups often suffice. With typical

microcontrollers and UARTs, direct connection is possible.

The Radio / data stream interface

A 32 byte software FIFO is implemented in both the transmit and receive sub-routine. At the

transmitting end this is used to allow for the transmitter start up time (about 3mS), while on receiving

end it buffers arriving packets to the constant output data rate. All timing and data formatting tasks

are handled by the internal firmware. The user need not worry about keying the transmitter before

sending data as the link is entirely transparent.

For transmission across the radio link data is formatted into packets, each comprising 3 bytes of data

and a sync code. If less than 3 bytes are in the transmit end FIFO then a packet is still sent, but idle

codes replaces the unused bytes. When the transmit end FIFO is completely emptied, then the

transmitter is keyed off.

Operation: Radio interface.

Raw data is not fed to the radios. A coding operation in the transmit sub-routine, and decoding in the

receiver, isolate the AC coupled, potentially noisy baseband radio environment from the datastream.

The radio link is fed a continuous tone by the modem. As in bi-phase codes, information is coded by

varying the duration consecutive half-cycles of this tone. In our case half cycles of 62.5us and 31.25us

are used. In idle (or 'preamble') state, a sequence of the longer cycles is sent (resembling an 8KHz tone).

A packet comprises the Synchronising (or address) part, followed by the Data part, made up of twelve

Groups (of four half cycles duration). Each Group encodes 2 data bits, so one byte is encoded by 4

Groups.

Radiometrix Ltd

TDL2A Data Sheet

page 4

TDL2R-433-4 Related Products

	TDL2R-433-4	TDL2T-433-9	TDL2R-433-9	TDL2A-433-4	TDL2A-433-9	TDL2T-433-4
Description	UHF Multi Channel Transparent Data Link Transceiver	UHF Multi Channel Transparent Data Link Transceiver	UHF Multi Channel Transparent Data Link Transceiver	UHF Multi Channel Transparent Data Link Transceiver	UHF Multi Channel Transparent Data Link Transceiver	UHF Multi Channel Transparent Data Link Transceiver

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