AT89S51-24 datasheet, PDF - EEWORLD Datasheet

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AT89S51-24: Description8-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP44; Categorysemiconductor The embedded processor and controller; File Size219KB，30 Pages; ManufacturerAtmel (Microchip)

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AT89S51-24 Overview

8-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP44

AT89S51-24 Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	44
Maximum operating temperature	70 Cel
Minimum operating temperature	0.0 Cel
Maximum supply/operating voltage	5.5 V
Minimum supply/operating voltage	4 V
Rated supply voltage	5 V
External data bus width	8
Number of input and output buses	32
Line speed	24 MHz
Processing package description	10 × 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, PLASTIC, MS-026ACB, TQFP-44
state	DISCONTINUED
Craftsmanship	CMOS
packaging shape	SQUARE
Package Size	FLATPACK, THIN PROFILE
surface mount	Yes
Terminal form	GULL WING
Terminal spacing	0.8000 mm
terminal coating	tin lead
Terminal location	Four
Packaging Materials	Plastic/Epoxy
Temperature level	COMMERCIAL
Address bus width	16
Number of digits	8
Maximum FCLK clock frequency	24 MHz
Microprocessor type	Microcontroller
ROM programming	FLASH

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Features

•

Compatible with MCS

-51 Products

•

4K Bytes of In-System Programmable (ISP) Flash Memory

•

– Endurance: 1000 Write/Erase Cycles

4.0V to 5.5V Operating Range

Fully Static Operation: 0 Hz to 33 MHz

Three-level Program Memory Lock

128 x 8-bit Internal RAM

32 Programmable I/O Lines

Two 16-bit Timer/Counters

Six Interrupt Sources

Full Duplex UART Serial Channel

Low-power Idle and Power-down Modes

Interrupt Recovery from Power-down Mode

Watchdog Timer

Dual Data Pointer

Power-off Flag

Fast Programming Time

Flexible ISP Programming (Byte and Page Mode)

Description

The AT89S51 is a low-power, high-performance CMOS 8-bit microcontroller with 4K

bytes of In-System Programmable Flash memory. The device is manufactured using

Atmel’s high-density nonvolatile memory technology and is compatible with the indus-

try-standard 80C51 instruction set and pinout. The on-chip Flash allows the program

memory to be reprogrammed in-system or by a conventional nonvolatile memory pro-

grammer. By combining a versatile 8-bit CPU with In-System Programmable Flash on

a monolithic chip, the Atmel AT89S51 is a powerful microcontroller which provides a

highly-flexible and cost-effective solution to many embedded control applications.

The AT89S51 provides the following standard features: 4K bytes of Flash, 128 bytes of

RAM, 32 I/O lines, Watchdog timer, two data pointers, two 16-bit timer/counters, a five-

vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and

clock circuitry. In addition, the AT89S51 is designed with static logic for operation

down to zero frequency and supports two software selectable power saving modes.

The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and

interrupt system to continue functioning. The Power-down mode saves the RAM con-

tents but freezes the oscillator, disabling all other chip functions until the next external

interrupt or hardware reset.

8-bit

Microcontroller

with 4K Bytes

In-System

Programmable

Flash

AT89S51

2487B–MICRO–12/03

Pin Description

VCC

GND

VDD

PWRVDD

PWRGND

Supply voltage (all packages except 42-PDIP).

Ground (all packages except 42-PDIP; for 42-PDIP GND connects only the logic core and the

embedded program memory).

Supply voltage for the 42-PDIP which connects only the logic core and the embedded program

memory.

Supply voltage for the 42-PDIP which connects only the I/O Pad Drivers. The application

board

MUST

connect both VDD and PWRVDD to the board supply voltage.

Ground for the 42-PDIP which connects only the I/O Pad Drivers. PWRGND and GND are

weakly connected through the common silicon substrate, but not through any metal link. The

application board

MUST

connect both GND and PWRGND to the board ground.

Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink eight

TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance

inputs.

Port 0 can also be configured to be the multiplexed low-order address/data bus during

accesses to external program and data memory. In this mode, P0 has internal pull-ups.

Port 0 also receives the code bytes during Flash programming and outputs the code bytes

during program verification.

External pull-ups are required during program verification.

Port 0

Port 1

Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can

sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the

internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being

pulled low will source current (I

) because of the internal pull-ups.

Port 1 also receives the low-order address bytes during Flash programming and verification.

Port Pin

P1.5

P1.6

P1.7

Alternate Functions

MOSI (used for In-System Programming)

MISO (used for In-System Programming)

SCK (used for In-System Programming)

Port 2

Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers can

sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the

internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being

pulled low will source current (I

) because of the internal pull-ups.

Port 2 emits the high-order address byte during fetches from external program memory and

during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this

application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external

data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Spe-

cial Function Register.

Port 2 also receives the high-order address bits and some control signals during Flash pro-

gramming and verification.

AT89S51

2487B–MICRO–12/03

AT89S51

Port 3

Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers can

sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the

internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being

pulled low will source current (I

) because of the pull-ups.

Port 3 receives some control signals for Flash programming and verification.

Port 3 also serves the functions of various special features of the AT89S51, as shown in the

following table.

Port Pin

P3.0

P3.1

P3.2

P3.3

P3.4

P3.5

P3.6

P3.7

Alternate Functions

RXD (serial input port)

TXD (serial output port)

INT0 (external interrupt 0)

INT1 (external interrupt 1)

T0 (timer 0 external input)

T1 (timer 1 external input)

WR (external data memory write strobe)

RD (external data memory read strobe)

RST

Reset input. A high on this pin for two machine cycles while the oscillator is running resets

the device. This pin drives High for 98 oscillator periods after the Watchdog times out. The

DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default

state of bit DISRTO, the RESET HIGH out feature is enabled.

Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during

accesses to external memory. This pin is also the program pulse input (PROG) during Flash

programming.

In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may

be used for external timing or clocking purposes. Note, however, that one ALE pulse is

skipped during each access to external data memory.

If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set,

ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled

high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution

mode.

ALE/PROG

PSEN

Program Store Enable (PSEN) is the read strobe to external program memory.

When the AT89S51 is executing code from external program memory, PSEN is activated

twice each machine cycle, except that two PSEN activations are skipped during each access

to external data memory.

EA/VPP

External Access Enable. EA must be strapped to GND in order to enable the device to fetch

code from external program memory locations starting at 0000H up to FFFFH. Note, however,

that if lock bit 1 is programmed, EA will be internally latched on reset.

EA should be strapped to V

for internal program executions.

This pin also receives the 12-volt programming enable voltage (V

) during Flash

programming.

XTAL1

XTAL2

Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

Output from the inverting oscillator amplifier

2487B–MICRO–12/03

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